參數(shù)資料
型號： ORT8850L
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 45/112頁
文件大?。?/td> 2417K
代理商： ORT8850L
Agere Systems Inc.
45
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Memory Map
(continued)
Table 12. Memory Map Descriptions
Bit/Register
Name(S)
Bit/
Register
Location
(Hex)
00 [0:7]
01 [0:7]
02 [0:7]
03 [0:7]
Register
Type
Reset
Value
(Hex)
Description
fixed rev [0:7]
fixed id lsb [0:7]
fixed id msb [7:0]
scratch pad [0:7]
sreg
05
80
80
00
NA
creg
The scratch pad has no function and is not used anywhere in
the core. However, this register can be written to and read from.
In order to write to registers in memory locations 06~7F, lockreg
msb and lockreg lsb must be respectively set to the values of
05 and 80. If the msb and lsb lockreg values are not set to {05,
80}, then any values written to the registers in memory loca-
tions 06~7F will be ignored.
After reset (both hard and soft), the core is in a write locked
mode. The core needs to be unlocked before it can be written
to.
Also note that the scratch pad register (03) can always be writ-
ten to as it is unaffected by write lock mode.
The global reset command is accessed via the pulse register in
memory address 06. The global reset command is a soft (soft-
ware initiated) reset. Nevertheless, the global reset command
will have the exact reset effect as a hard (RST_N pin) reset.
lockreg msb [0:7]
lockreg lsb [0:7]
04 [0:7]
05 [0:7]
creg
00
00
global reset com-
mand
06 [0]
preg
NA
Device Register Blocks
lvds lpbk control
08 [0]
creg
0
ext prot sw en
08 [3]
creg
0
“
rx toh frame
”
and
“
rx toh clk enable
”
hiz control
08 [4]
creg
0
CDR
0
No loopback.
LVDS loopback, transmit to receive on. Serieal data is looped
back to the rx serial input.
1
ext port
sw en
LVDS Protection Switching
0
-
MUX is controlled by software (1 control bit per MUX) reg 09
.
- Output buffers
’
enables are controlled by software (1 control bit per chan-
nel) reg 20, 38, 50, 68, 80, 98, b0, c8.
1
MUX is controlled by hardware pins.
lvds_Prot_Switch_[aa,ab,ac,ad,ba,bb,bc,bd]
0
TOH_CK_FP_EN = 0, can be used to 3-state RX_TOH_CK_EN and RX_TOH_FP signals.
1
Function mode.
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