參數(shù)資料
型號(hào)： ORT8850H
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù)： 73/112頁(yè)
文件大?。?/td> 2417K
代理商： ORT8850H
Agere Systems Inc.
73
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Pin Information
(continued)
Table 31. Embedded Core/FPGA Interface Signal Description
(continued)
Pin Name
I/O
Description
STM Clock and Control
sys_fp
line_fp
fpga_sysclk
I
I
System frame pulse for transmitter section.
Line frame pulse for receiver section.
System clock (sys_clk). This signal is routed onto a primary clock net inside the
FPGA, with very low skew.
STM channel protection enable for channels aa and ab. Active-high.
STM channel protection enable for channels ac and ac. Active-high.
STM channel protection enable for channels ba and bb. Active-high.
STM channel protection enable for channels bc and bd. Active-high.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
LVDS buffer redundancy select for rx channel aa. Active-high for redundant link.
During powerup and FPGA configuration sequence, the core_ready is held low. At
the end of FPGA configuration, the core_ready will be held low for six clock
(sys_clk) cycles and then go active-high. Flag indicates that the embedded core is
out of its reset state.
Recovered clock for STM slice A, channel A.
Recovered clock for STM slice A, channel B.
Recovered clock for STM slice A, channel C.
Recovered clock for STM slice A, channel D.
Recovered clock for STM slice B, channel A.
Recovered clock for STM slice B, channel B.
Recovered clock for STM slice B, channel C.
Recovered clock for STM slice B, channel D.
O
prot_switch_aa
prot_switch_ac
prot_switch_ba
prot_switch_bc
lvds_prot_aa
lvds_prot_ab
lvds_prot_ac
lvds_prot_ad
lvds_prot_ba
lvds_prot_bb
lvds_prot_bc
lvds_prot_bd
core_ready
I
I
I
I
I
I
I
I
I
I
I
I
O
cdr_clk_aa
cdr_clk_ab
cdr_clk_ac
cdr_clk_ad
cdr_clk_ba
cdr_clk_bb
cdr_clk_bc
cdr_clk_bd
O
O
O
O
O
O
O
O
8B/10B Mode Signals
tx_k_ctrl_aa
tx_k_ctrl_ab
tx_k_ctrl_ac
tx_k_ctrl_ad
tx_k_ctrl_ba
tx_k_ctrl_bb
tx_k_ctrl_bc
tx_k_ctrl_bd
I
I
I
I
I
I
I
I
K control bit for channel AA.
K control bit for channel AB.
K control bit for channel AC.
K control bit for channel AD.
K control bit for channel BA.
K control bit for channel BB.
K control bit for channel BC.
K control bit for channel BD.
相關(guān)PDF資料
PDF描述
ORT8850L Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
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ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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