參數(shù)資料
型號： ORT8850H
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 47/112頁
文件大小： 2417K
代理商： ORT8850H
Agere Systems Inc.
47
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Memory Map
(continued)
Table 12. Memory Map Descriptions
(continued)
Bit/Register Name(S)
Bit/
Register
Location
(Hex)
Register
Type
Reset
Value
(Hex)
Description
input/output parallel bus
parity control
0C [5]
creg
1
scrambler/descrambler
control
0C [6]
creg
1
transmit B1 error insert
mask [0:7]
0F [0:7]
creg
00
ch 1 int
ch 2 int
ch 3 int
ch 4 int
per device int
enable/mask register for
ch 1-4 + device[4:0]
ch 5 int
ch 6 int
ch 7 int
ch 8 int
enable/mask register for
ch 5-8 [0:3]
10 [0]
10 [1]
10 [2]
10 [3]
10 [4]
11 [0:4]
14 [0]
14 [1]
14 [2]
14 [3]
15 [0:3]
isreg
isreg
isreg
isreg
isreg
iereg
isreg
isreg
isreg
isreg
iereg
0
0
0
0
0
0
0
0
0
0
0
Consolidation interrupts. 1 = interrupt, 0 = no interrupt.
frame offset error flag
write to locked register
error flag
enable/mask register [0:1]
12 [0]
12 [1]
13 [0:1]
iareg
iareg
iereg
0
0
0
If in the receive direction the phase offset between any two
channels exceeds 17 bytes, then a frame offset error event
will be issued. This condition is continuously monitored.
If the core memory map has not been unlocked (by writing
to the lock registers), and any address other than the lock-
reg registers or scratch pad register is written to, then a
“
write to locked register
”
event will be generated.
STM A mode control
STM B mode control
16 [2:3]
16 [0:1]
creg
creg
0
0
00 - Quad STS-12 or STS-48.
01 - Quad STS-3.
10 - Quad STS-1.
00 - Quad STS-12 or STS-48.
01 - Quad STS-3.
10 - Quad STS-1.
individual alignment
resync register
17 [0:7]
creg
0
Write 1 to resync stream.
group alignment resync
register
18 [0:7]
creg
0
Write 1 to resync selected grouping.
0
Even parity.
1
Odd parity.
0
no rx direction, descramble / tx direction scramble.
1
In rx direction, descramble channel after SONET frame recov-
ery.
In tx direction, scramble data just before parallel-to-serial con-
version.
0
No error insertion.
1
Invert corresponding bit in B1 byte.
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ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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