參數(shù)資料
型號(hào)： ORT8850H
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁數(shù)： 38/112頁
文件大小： 2417K
代理商： ORT8850H
38
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
RapidIO
Interface to Pi-Sched
(continued)
Table 9. Signals Used as Register Bits
Memory Map
Definition of Register Types
There are six structural register elements: sreg, creg, preg, iareg, isreg, and iereg. There are no mixed registers in
the chip. This means that all bits of a particular register (particular address) are structurally the same. All of these
registers are accessed via the FPGA system bus which, in turn, can be accessed by the MPI block or through
FPGA logic.
Register Bit(s)
OSHLBENB
Description
Used during the internal built-in self-test mode. Indicates that the single-ended versions of the
transmit module outputs should be looped back into the single-ended inputs of the receive
module.
OSHLENB = 0: No loopback.
OSHLENB = 1: Loopback.
This value indicates the minimum cell size and will be used to detect cell underrun errors. This
value should be set and stable prior to initialization of operation and stable thereafter.
Enables the internal self-test of the
RapidIO
block. Two loopback paths exist during test, inter-
nal and external. During both tests, data is passed through all modules and verified.
Indicates the completion of the internal test. Only valid during a test when OTESTENB is high.
ITESTDONE = 0: Test running.
ITESTDONE = 1: Test complete.
Indicates the success of the internal test. This signal is valid only when ITESTDONE is high.
ITESTPASS = 0: Test failed.
ITESTPASS = 1: Test passed.
Active-low. 3-state override for transmit outputs. This signal is ignored during reset, but takes
priority over all 3-state control signals when active.
OCELLSIZE[4:0]
OTESTENB
ITESTDONE
ITESTPASS
TRISTN
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