參數(shù)資料
型號(hào)： ORT8850H
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù)： 25/112頁(yè)
文件大?。?/td> 2417K
代理商： ORT8850H
Agere Systems Inc.
25
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Backplane Transceiver Core Detailed Description
(continued)
Transport Overhead Extraction
Transport overhead is extracted from the receive data stream by the TOH extract block. The incoming data gets
loaded into a 36-byte shift register on the system clock domain. This, in turn, is clocked onto the TOH clock domain
at the start of the SPE time, where it can be clocked out.
During the SPE time, the receiver TOH frame pulse is generated, RX_TOH_FP, which indicates the start of the row
of 36 TOH bytes. This pulse, along with the receive TOH clock enable, RX_TOH_CK_EN, as well as the TOH data,
are all launched on the rising edge of the TOH clock TOH_CLK.
TOH Byte Ordering
The TOH processor is responsible for dropping all TOH bytes of each channel through one of four corresponding
serial ports. The four TOH serial ports are synchronized to the TOH clock (the same clock that is being used by the
serial ports on the transmitter side). This free-running TOH clock is provided to the core by external circuitry and
operates at a minimum frequency of 25 MHz and a maximum frequency of 77.76 MHz. Data is transferred over
serial links in a bursty fashion as controlled by the Rx TOH clock enable signal, which is generated by the ASIC
and common to the four channels. All TOH bytes of STS-12 streams are transferred over the appropriate serial link
in the same order in which they appear in a standard STS-12 frame. Data transfer should be preformed on a row-
by-row basis such that internal data buffering needs is kept to a minimum. Data transfers on the serial links will be
synchronized relative to the Rx TOH frame signal.
Receiver TOH Reconstruction
Receiver TOH reconstruction on output parallel bus is as shown in the following table (if the pointer mover is not
bypassed).
Table 4. Receiver TOH (Output Parallel Bus)
On the TOH serial port, all TOH bytes are dropped as received on the LVDS input (MSB first). The only exception
is the most significant bit of byte A1 of STS#1, which is replaced with an even parity bit. This parity bit is calculated
over the previous TOH frame. Also, on AIS-L (either resulting from LOF or forced through software), all TOH bits
are forced to all ones with proper parity (parity automatically ends up being set to 1 on AIS-L).
Special TOH Byte Functions
K1 and K2 Handling.
The K1 and K2 bytes are used in automatic protection switch (APS) applications. K1 and K2
bytes can be optionally passed through the pointer mover under software control, or can be set to zero with the
other TOH bytes.
A1 and A2 Handling.
As discussed previously, the A1 and A2 bytes are used for a framing header. A1 and A2
bytes are always regenerated and set to hexadecimal F6 and 28, respectively.
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A1
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
A2
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H1
0
0
0
H2
K1
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H2
0
0
0
H3
K2
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
H3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Regenerated bytes.
Regenerated bytes (under pointer generator control, SS bits must be transparent, AIS-P must be supported).
Bytes taken from elastic store buffer, on negative stuff opportunity-else, forced to all zeros.
Transparent or all zeros (K1/K2 are either taken from K1/K2 buffer or forced to all zeros-soft, control). In transparent mode, AIS-L must be supported.
All zero bytes.
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ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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