參數(shù)資料
型號(hào)： ORT8850H
英文描述： Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
中文描述： 現(xiàn)場(chǎng)可編程系統(tǒng)芯片（促進(jìn)文化基金）8通道x 850 Mbits /秒背板收發(fā)器
文件頁(yè)數(shù)： 6/112頁(yè)
文件大?。?/td> 2417K
代理商： ORT8850H
6
Agere Systems Inc.
Data Sheet
August 2001
Eight-Channel x 850 Mbits/s Backplane Transceiver
ORCA
ORT8850 FPSC
Programmable FPGA Features
(continued)
I
Built-in testability:
—
Full boundary scan (
IEEE
1149.1 and Draft
1149.2 JTAG).
—
Programming and readback through boundary
scan port compliant to
IEEE
Draft 1532:D1.7.
—
TS_ALL testability function to 3-state all I/O pins.
—
New temperature-sensing diode.
I
New cycle stealing capability allows a typical 15% to
40% internal speed improvement after final place
and route. This feature also enables compliance with
many setup/hold and clock to out I/O specifications
and may provide reduced ground bounce for output
buses by allowing flexible delays of switching output
buffers.
Programmable Logic System Features
I
PCI local bus compliant for FPGA I/Os.
I
Improved
PowerPC
860 and
PowerPC
II high-speed
synchronous microprocessor interface can be used
for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA logic, RAMs, and embedded back-
plane transceiver blocks. Glueless interface to
synchronous
PowerPC
processors with user-config-
urable address space provided.
I
New embedded
AMBA
specification 2.0 AHB sys-
tem bus (
ARM
processor) facilitates communica-
tion among the microprocessor interface,
configuration logic, embedded block RAM, FPGA
logic, and backplane transceiver logic.
I
New
network PLLs meet ITU-T G.811 specifications
and provide clock conditioning for DS-1/E-1 and
STS-3/STM-1 applications.
I
Flexible general-purpose PPLLs offer clock multiply
(up to 8x), divide (down to 1/8x), phase shift, delay
compensation, and duty cycle adjustment combined.
I
Variable size bused readback of configuration data
capability with the built-in microprocessor interface
and system bus.
I
Internal, 3-state, and bidirectional buses with simple
control provided by the SLIC.
I
New clock routing structures for global and local
clocking significantly increases speed and reduces
skew (<200 ps for OR4E4).
I
New local clock routing structures allow creation of
localized clock trees.
I
New edge clock routing supports at least six fast
edge clocks per side of the device
I
New double-data rate (DDR) and zero-bus turn-
around (ZBT) memory interfaces support the latest
high-speed memory interfaces.
I
New 2x/4x uplink and downlink I/O capabilities inter-
face high-speed external I/Os to reduced speed
internal logic.
I
ORCA
Foundry 2000 development system software.
Supported by industry-standard CAE tools for design
entry, synthesis, simulation, and timing analysis.
I
Meets universal test and operations PHY interface
for ATM (UTOPIA) Levels 1, 2, and 3. Also meets
proposed specifications for UTOPIA Level 4 for
10 Gbits/s interfaces.
I
Two new edge clock routing structures allow up to
seven high-speed clocks on each edge of the device
for improved setup/hold and clock to out perfor-
mance.
相關(guān)PDF資料
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ORT8850H-1BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BM680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-1BMN680I 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
ORT8850H-2BM680C 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門(mén)陣列 16192 LUT 297 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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