參數(shù)資料
型號: OR3TP12-6PS240
英文描述: Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
中文描述: 用戶可編程ASIC的特殊功能
文件頁數(shù): 95/128頁
文件大?。?/td> 2450K
代理商: OR3TP12-6PS240
Lucent Technologies Inc.
Lucent Technologies Inc.
95
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
Timing Characteristics
(continued)
Table 33. OR3TP12 PCI and FPGA Interface Clock Operation Frequencies
OR3TP12 Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C < T
A
< 70 °C.
* The PCI clock frequency is based on the internal register to register frequency and the 66 MHz PCI I/O specifications.
The Maximum User Interface Clock frequencies are values based on registering all signals at the FPGA/ASIC boundary. This number
will be lower depending on the design implementation and number of FPGA logic levels into and out of the ASIC.
This is the typical operating frequency for a real design that does not register signals at the FPGA/ASIC boundary.
Table 34. OR3TP12 FPGA to PCI, and PCI to FPGA, Combinatorial Path Delays
OR3TP12 Commercial: V
DD
= 3.0 V to 3.6 V, 0 °C < T
A
< 70 °C.
Notes:
On the FPGA to PCI combinatorial path delays, they include the ASIC path delay and the output buffer delay under a
10pf load. They do not include the interbuf delay on the FPGA side.
On the PCI to FPGA combinatorial path delays, they include the ASIC input buffer delay, and ASIC path delay entering the
FPGA. They do not include the interbuf delay on the FPGA side.
Description
(T
I
= 85 °C, V
DD
= min, V
DD
2 = min)
Speed
–7
Unit
Signal
Min
0
0
0
Typ
—*
Max
66*
66
66
Clk
(PCI clock)
fclk1
(user interface clock)
fclk2
(user interface clock)
MHz
MHz
MHz
Description
(T
I
= 85 °C, V
DD
= min, V
DD
2 = min)
Min
Max
Unit
Source
Destination
intan
(PCI Side)
pciclk
(FPGA Side)
pci_rstn
(FPGA Side)
pci_intan
(FPGA Side)
clk
(PCI Side)
rstn
(PCI Side)
4.601
4.544
2.442
ns
ns
ns
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