參數(shù)資料
型號(hào)： OR3TP12-6PS240
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
中文描述： 用戶(hù)可編程ASIC的特殊功能
文件頁(yè)數(shù)： 119/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240
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Lucent Technologies Inc.
Lucent Technologies Inc.
119
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
Package Thermal Characteristics
Summary
There are three thermal parameters that are in com-
mon use:
Θ
JA
,
ψ
JC, and
Θ
JC
. It should be noted that all
the parameters are affected, to varying degrees, by
package design (including paddle size) and choice of
materials, the amount of copper in the test board or
system board, and system airflow.
Θ
JA
This is the thermal resistance from junction to ambient
(theta-JA, R-theta, etc.).
where T
J
is the junction temperature, T
A
is the ambient
air temperature, and Q is the chip power.
Experimentally,
Θ
JA
is determined when a special ther-
mal test die is assembled into the package of interest,
and the part is mounted on the thermal test board. The
diodes on the test chip are separately calibrated in an
oven. The package/board is placed either in a JEDEC
natural convection box or in the wind tunnel, the latter
for forced convection measurements. A controlled
amount of power (Q) is dissipated in the test chip’s
heater resistor, the chip’s temperature (T
J
) is deter-
mined by the forward drop on the diodes, and the ambi-
ent temperature (T
A
) is noted. Note that
Θ
JA
is
expressed in units of °C/watt.
ψ
JC
This JEDEC designated parameter correlates the junc-
tion temperature to the case temperature. It is generally
used to infer the junction temperature while the device
is operating in the system. It is not considered a true
thermal resistance, and it is defined by:
where T
C
is the case temperature at top dead center,
T
J
is the junction temperature, and Q is the chip power.
During the
Θ
JA
measurements described above,
besides the other parameters measured, an additional
temperature reading, T
C
, is made with a thermocouple
attached at top-dead-center of the case.
ψ
JC
is also
expressed in units of °C/watt.
Θ
JC
This is the thermal resistance from junction to case. It
is most often used when attaching a heat sink to the
top of the package. It is defined by:
The parameters in this equation have been defined
above. However, the measurements are performed with
the case of the part pressed against a water-cooled
heat sink to draw most of the heat generated by the
chip out the top of the package. It is this difference in
the measurement process that differentiates
Θ
JC
from
ψ
JC.
Θ
JC
is a true thermal resistance and is expressed
in units of °C/watt.
Θ
JB
This is the thermal resistance from junction to board
(
Θ
JB
). It is defined by:
where T
B
is the temperature of the board adjacent to a
lead measured with a thermocouple. The other param-
eters on the right-hand side have been defined above.
This is considered a true thermal resistance, and the
measurement is made with a water-cooled heat sink
pressed against the board to draw most of the heat out
of the leads. Note that
Θ
JB
is expressed in units of
°C/watt, and that this parameter and the way it is mea-
sured are still in JEDEC committee.
FPGA Maximum Junction Temperature
Once the power dissipated by the FPGA has been
determined (see the Estimating Power Dissipation sec-
tion), the maximum junction temperature of the FPGA
ating of the device from the 85 °C junction temperature
used in all of the delay tables is needed. Using the
maximum ambient temperature, T
Amax
, and the power
dissipated by the device, Q (expressed in °C), the max-
imum junction temperature is approximated by:
T
Jmax =
T
Amax
+ (Q
Θ
JA
)
Table 45 lists the thermal characteristics for all pack-
ages used with the ORCA OR3TP12 Series of FPGAs.
Θ
JA
J
T
T
A
–
Q
=
ψ
JC
J
T
T
C
–
Q
=
Θ
JC
J
T
T
C
–
Q
=
Θ
JB
J
T
T
B
–
Q
=
相關(guān)PDF資料
PDF描述
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
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