參數資料
型號： OR3TP12-6PS240
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁數： 67/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240
Lucent Technologies Inc.
Lucent Technologies Inc.
67
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Target Controller Detailed
Description
(continued)
When executing a burst Target read, or on a 64-bit bus
(
pci_64-bit
= 1), the read data transferred from the
FPGA application must be aligned on 64-bit address
boundaries, which may require transferring extra pad-
ding data to proper fill the FIFOs for activity on 32-bit
PCI buses. For transfers starting at an odd 32-bit PCI
address (
ad2
= 1), the FPGA application will transfer a
extra 32-bit padding data word at the beginning of the
read data phase. For burst transfers starting at an even
PCI address (
ad2
= 0) with an odd number of 32-bit
data words, a extra 32-bit padding data word will be
transferred at the end of the data phase. Padding data
word can be any data words.
For single 32-bit transactions (burst indication bit deas-
serted) on a 32-bit PCI bus (
pci_64bit
= 0), the Target
FIFO interface handles all data alignment. The
received address is valid with the data phase aligning
to the address. No extra padding of data is necessary.
At some times, the FPGA application may not have
valid data to transfer to the Target read FIFO or the
read data FIFOs may be filled, therefore
trdataenn
will
be deasserted. If the external Master disconnects dur-
ing this time,
trlastcycn
will not be produced. In this
situation, the FPGA application must monitor the signal
t_ready
for an indication that the external Master is ter-
minating the Target transaction. When
t_ready
is deas-
serted, the FPGA application will need to assert
trdataenn
to receive
trlastcycn
and properly reset the
Target FIFO interface. During the time that
t_ready
is
deasserted, the Target is clearing the Target read
FIFOs and no data will be transferring to the PCI bus.
Any read data transferred will be ignored during this
time.
Burst transfers are performed as continuous data
phases if read data is available in the Target read data
FIFO. At completion of Target read bursts, there may
result a discarding of unused data elements supplied in
excess of the external Master transaction’s needs. All
data within the Target read FIFOs is cleared after Mas-
ter termination.
Target Read FIFO Hold
The signal
trpcihold
can be asserted to delay the start
of transfer of data during a Target read operation, i.e.,
trdyn
asserted. While
trpcihold
is active, read data
can be transferred from the FPGA application into the
Target read FIFOs. When the Target read FIFOs
become full or
trpcihold
is deasserted, the Target read
operation will begin on the PCI bus. Use of this signal
can result in more efficient utilization of PCI bus band-
width by causing up to a full buffer contents to be
bursted, without wait-states, whenever the external
Master accesses the Target.
FIFO Full/Almost Full
When the Target read FIFO contains four or fewer 64-
bit empty locations, the Target FIFO interface asserts
tr_afulln
, the almost full indicator. This allows some
latency to exist in the FPGA’s response without risking
overfilling the FIFO. When all locations in the Target
read FIFO are full, the Target asserts
tr_fulln
, the full
indicator. Since the data can be simultaneously written
to and read from the Target read data FIFO, both
tr_afulln
and
tr_fulln
can change states in either
direction multiple times in the course of a burst data
transfer.
Termination
Target read termination will be by normal Master termi-
nation, disconnect associated with a empty Target read
data FIFO, retry associated with a pending Target
transaction, or a reset by
rstn
.
On the Target FIFO interface,
trlastcycn
signals when
the external Master has gathered all of the necessary
data from the Target read FIFO, even if extra data
remains in the Target read FIFO. The Target FIFO inter-
face signals end of transaction to the FPGA application
by deasserting
treqn
for at least one clock. If
treqn
subsequently reasserts, this indicates a new, unrelated
transaction.
Reset
The FPGA application can apply a reset signal to place
the Target FIFO interface logic in a known state, clear-
ing the Target FIFOs and resetting
tstatecntr
. The
reset signal,
tfifoclrn
, is asynchronous and therefore
should be asserted for a minimum of one clock cycle
and deasserted for a minimum of one clock cycle
before continuing.
It is not recommended to assert
tfifoclrn
while a cur-
rent PCI transaction is in progress (
treqn
is asserted),
since proper PCI bus termination is not guaranteed.
Only
rstn
will reset the internal Target PCI state
machines, while a PCI transaction is in progress.
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