參數(shù)資料
型號(hào)： OR3TP12-6PS240
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
中文描述： 用戶可編程ASIC的特殊功能
文件頁(yè)數(shù)： 37/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12-6PS240
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Lucent Technologies Inc.
Lucent Technologies Inc.
37
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Master Controller
Detailed Description
(continued)
Write Data Phase
The FPGA application begins the write data phase by
deasserting
maenn
and asserting
mwdataenn
. On
every clock cycle that
mwdataenn
is asserted, the
FPGA application will transfer write data and its associ-
ated byte enables into the Master write data FIFO
(sixty-four 32-bit words; thirty-two 64-bit words) via bus
mwdata
(quad- port mode) or
datafmfpga
(dual-port
mode).
mwdataenn
must not be asserted when the
write data FIFOs are full (
mw_fulln
is asserted). Note
that
mw_fulln
can be updated on the same clock edge
as
mwdataenn
is sampled.
The distinction between a burst write and a single
access is provide by the
mwlastcycn
signal instead of
using a burst length. This allows the FPGA application
to maintain control over the length of the Master write
burst. When
mwlastcycn
is asserted, this informs the
Master FIFO interface of the end of the write data
phase.
mwlastcycn
will be deasserted for every data
element except the last element on bus
mwdata
(quad-
port mode) or
datafmfpga
(dual-port mode).
mwlast-
cycn
can remain asserted throughout a single (non-
burst) Master write. For example, to perform a single
32-bit word transfer in dual-port mode,
mwlastcycn
would be asserted during the entire data phase, since
the last data phase is the only data phase. Note if
mwlastcycn
is asserted,
mwdataenn
must be
asserted.
When executing a burst Master write or on a 64-bit bus
(
pci_64bit
= 1), the write data transferred from the
FPGA application is aligned on 64-bit address bound-
aries, which may require padding of write data to prop-
erly fill/align the write data FIFOs. For transfers starting
at an odd 32-bit PCI address (
ad2
= 1), this will require
a 32-bit padding data word at the beginning of the write
data phase. Padding of FIFO is accomplished by trans-
ferring a data word with its byte enables deasserted. In
64-bit transfers, the padding word will be place on the a
32-bit segment with its byte enables deasserted and
the external Target will ignore it. For 32-bit wide data
transfers, this padding word will be ignored and not
transferred to the PCI bus.
For single 32-bit transaction on 32-bit buses
(
pci_64bit
= 0), the Master FIFO Interface will perform
the proper data alignment. The FPGA application only
needs to transfer the valid 32-bit data word during the
data phase.
FIFO Full/Almost Full
When the Master write data FIFO contains four or
fewer 64-bit empty locations, the Master FIFO interface
asserts
mw_afulln
, the almost full indicator. This
allows some latency to exist in the FPGA’s response
without risking overfilling the FIFO. When all locations
in the Master write data FIFO are full, the Master FIFO
interface asserts
mw_fulln
, the FIFO full indicator.
Since data can be simultaneously written to and read
from the Master write FIFO, both
mw_afulln
and
mw_fulln
can change states in either direction multiple
times in the course of a burst transfer.
Master Write Hold
The signal
mwpcihold
can be asserted to delay the
initiation of a Master write operation, i.e.,
reqn
asserted, until an greater amount of data is available in
the write data FIFOs. Normally, the Master write opera-
tion would begin after the first write data word is
received by the Master FIFO interface. While
mwpci-
hold
is active, write data can be transferred from the
FPGA application into the write FIFOs. When the Mas-
ter write FIFOs become full or
mwpcihold
is deas-
serted, the Master write operation will begin on the PCI
bus (
reqn
asserted).
mwpcihold
must be deasserted
at least two
pciclks
before
mwlastcycn
is asserted,
which indicates the end of the write data phase.
Use of this signal can result in more efficient utilization
of PCI bus bandwidth by causing a full buffer contents
to be bursted, without wait-states, after the PCI bus is
claimed.
Wait-States
The Master will not insert wait-states into a write trans-
fer, as long as the Master write data FIFO is nonempty.
If the Master write data FIFO becomes empty before
mwlastcycn
was asserted by the FPGA application,
wait-states will be inserted until more write data is pro-
vided or the external Target disconnects. If the FPGA
application cannot provide subsequent data to the
Master write data FIFO within an eight
pciclk
period, it
is recommended to end the data phase by asserting
mwlastcycn
and
mwdataenn
, along with a valid data
word, to avoid excessive wait-states insertion.
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