參數(shù)資料
型號： OR3TP12-6BA256I
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁數(shù)： 6/128頁
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256I
ORCAOR3TP12 FPSC
Embedded Master/Target PCI Interface
Data Sheet
March 2000
6
L Lucent Technologies Inc.
PCI Bus Core Highlights
(continued)
I
Generates interrupts on
intan
as directed by the
FPGA.
I
Provisions for 64-bit PCI bus capability in 352-pin
PBGA package.
I
Automatically detects 5 V or 3.3 V PCI bus signaling
environment and provides appropriate I/O signal
clamping.
I
Pinout compatible with the ORCA PCI Master/Target
Customer Solution Core V2.0 for OR2C/TxxA or
ORCASeries 3 FPGAs.
I
Ideally suited for such applications as:
— PCI-based graphics/video/multimedia.
— Bridges to ISA/EISA/MCA, LAN, SCSI, Ethernet,
ATM, or other bus architectures.
— High-bandwidth data transfer in proprietary sys-
tems.
FPSC Highlights
I
Implemented as an embedded core into the
advanced Series 3+ ORCA FPSC architecture.
I
Allows the user to integrate the core with up to 60K
gates of programmable logic, all in one device, and
provides up to 187 user I/O pins in addition to the
PCI interface pins.
I
FPGA portion retains all of the features of the ORCA
Series 3 FPGA architecture:
— High-performance, cost-effective, 0.3 μm
4-level metal technology, with a migration plan to
0.25 μm technology.
— Twin-quad programmable function unit (PFU)
architecture with eight 16-bit look-up tables
(LUTs) per PFU, organized in two nibbles for use
in nibble- or byte-wide functions. Allows for mixed
arithmetic and logic functions in a single PFU.
— Softwired LUTs (SWL) allow fast cascading of up
to three levels of LUT logic in a single PFU for up
to 40% speed improvement (-5 speed grade).
— Supplemental logic and interconnect cell (SLIC)
provides 3-statable buffers, up to 10-bit decoder,
and PAL*-like AND-OR-INVERT (AOI) in each
programmable logic cell (PLC).
— Up to three ExpressCLK inputs allow extremely
fast clocking of signals on- and off-chip plus
access to internal general clock routing.
— Dual-use microprocessor interface (MPI) can be
used for configuration, readback, device control,
and device status, as well as for a general-pur-
pose interface to the FPGA. Glueless interface to
i960
and PowerPC
processors with user-config-
urable address space provided.
— Programmable clock manager (PCM) adjusts
clock phase and duty cycle for input clock rates
from 5 MHz to 120 MHz. The PCM may be com-
bined with FPGA logic to create complex func-
tions, such as digital phase-locked loops (DPLL),
frequency counters, and frequency synthesizers
or clock doublers. Two PCMs are provided per-
device.
— True
internal 3-state, bidirectional buses with sim-
ple control provided by the SLIC.
— 32
×
4
RAM per PFU, configurable as single or
dual-port at >170 MHz (-5 speed). Create large,
fast RAM/ROM blocks (128
×
8 in only eight
PFUs) using the SLIC decoders as bank drivers.
— Built-in boundary scan (IEEE
§
1149.1 JTAG) and
TS_ALL testability function to 3-state all I/O pins.
I
High-speed
on-chip interface provided between
FPGA logic and embedded core to reduce bottle-
necks typically found when interfacing off-chip.
I
Supported in three packages: 240-pin SQFP2,
256-pin PBGA, and 352-pin PBGA (64-bit PCI in
352-pin PBGA only).
Software Support
I
Supported by ORCA Foundry software and third-
party CAE tools for implementing ORCA Series 3+
devices and simulation/timing analysis with embed-
ded PCI bus core.
I
PCI bus core configuration options and simulation
models generated by FPSC configuration manager
utility in ORCAFPSC Design Kit software.
I
Timing constraints provided for interface between
PCI bus core and FPGA logic.
*
PALis a trademark of Advanced Micro Devices, Inc.
i960is a registered trademark of Intel Corporation.
PowerPC is a registered trademark of International Business
Machines Corporation.
§
IEEEis a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR3TP126BA256I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR3TP12-6BA352I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC
OR3TP126BAN256-DB 制造商:Lattice Semiconductor Corporation 功能描述:
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