參數(shù)資料
型號(hào)： OR3TP12-6BA256I
英文描述： Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
中文描述： 用戶可編程ASIC的特殊功能
文件頁(yè)數(shù)： 23/128頁(yè)
文件大?。?/td> 2450K
代理商： OR3TP12-6BA256I
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Lucent Technologies Inc.
Lucent Technologies Inc.
23
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
Symbol
I/O
Description
Clock
Domain
Master Write Data FIFO Signals
(continued)
mwdata[17:0]
(quad-port mode)
or
datafmfp-
gax[3:0]
,
datafmfpga[31:0]
(dual-port mode)
O
Depending on the OR3TP12 configuration, only one of these buses will be
available to the FPGA application. For Master operations, these buses will
carry the same information, but in different sizes and different bit lanes as sum-
marized below:
Quad-Port Mode
a. Master Command.
Control data decoded by the Master Controller and
FIFO interface
Repeat Burst Length:
mwdata[17]
Dual-Address Indication:
mwdata[16]
Unused:
mwdata[15:13]
Holding Reg. Selector:
mwdata[12]
Master Rd. Byte Enables:
mwdata[11:4]
Master Command Code:
mwdata[3:0]
b. Master Start Address: 32- or 64-bit PCI start address.
Unused:
mwdata[17:16]
Address:
mwdata[15:0]
c. Master Read Burst Count (18 bits): Number of 64-bit words.
Burst Length[17:16]:
mwdata[17:16]
Burst Length[15:0]:
mwdata[15:0]
d. Master Write Data: Write data to PCI bus.
Write Enables:
mwdata[17:16]
Data:
mwdata[15:0]
Master Read Data FIFO Signals
mrdataenn
O
Master Read FIFO Data Output Enable.
This active-low signal enables data
from the Master read data FIFOs onto bus
mrdata
(quad-port mode) or
datatofpga
(dual-port mode,
fifo_sel
= 0).
mrdataenn
must never be asserted
if the Master read FIFO is empty (
mr_emptyn
= 0)
mrdata[17:0]
(quad-port mode)
or
datatofpgax[3:0
],
datatofpga[31:0]
(dual-port mode)
Unused:
Data:
mr_aemptyn
I
Master Read Data FIFO Almost Empty.
This active-low signal indicates that
only four more 64-bit data locations are available to be read from the Master
read data FIFO.
mr_emptyn
I
Master Read Data FIFO Empty.
This active-low signal indicates that the Mas-
ter read data FIFO is empty.
mrdataenn
should never be asserted when
mr_emptyn
is active.
mrlastcycn
I
Master Read Last Data Cycle.
This active-low signal is asserted to indicate
that the accompanying Master read data is the final data word for this opera-
tion.
mrdataenn
must be asserted to receive
mrlastcycn
.
Dual-Port Mode
datafmfpgax[3]
datafmfpgax[2]
datafmfpga[31:29]
datafmfpga[28]
datafmfpga[27:20]
datafmfpga[19:16]
datafmfpgax[3:0]
datafmfpga[31:0]
datafmfpgax[1:0]
datafmfpga[15:0]
datafmfpgax[3:0]
datafmfpga[31:0]
fclk
*
fclk
*
I
Depending on the OR3TP12 configuration, only one of these buses will be
available to the FPGA application. For Master operations, these buses will
carry the same information, but in different sizes as summarized below:
Quad-Port Mode
Master Read Data (16/32 bits)
mrdata[17:16]
mrdata[15:0]
Dual-Port Mode (
fifo_sel
= 0)
datatofpgax[3:0]
datatofpga[31:0]
fclk
*
fclk
*
fclk
*
fclk
*
* The source of the clock (
fclk1
or
fclk2
) for the FIFO interface (Master or Target) is selected in the FPSC configuration manager.
PCI Bus Core Detailed Description
(continued)
Table 6. Embedded Core/FPGA Interface Signals
(continued)
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
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參數(shù)描述
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