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參數(shù)資料
| 型號(hào)： | OR3TP12-6BA256I |
| 英文描述： | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE |
| 中文描述： | 用戶可編程ASIC的特殊功能 |
| 文件頁數(shù)： | 15/128頁 |
| 文件大小： | 2450K |
| 代理商： | OR3TP12-6BA256I |
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Lucent Technologies Inc.
Lucent Technologies Inc.
15
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
0111
Memory Write
√
√
Fully implemented.
Target:
Writes are posted, bursting is allowed, and wait-
states generation is controllable. When the Target write
FIFO is full, the next data phase will be disconnected with-
out data (
twburstpendn
= 1), or up to eight wait-states can
be inserted (
twburstpendn
= 0). After the PCI bus transac-
tion completes and the FPGA application empties the Tar-
get write FIFO, the Target write logic is cleared.
Master:
Single and burst operations are allowed.
Target ignores, per PCI Specification Section 3.1.1.
Target ignores, per PCI Specification Section 3.1.1.
Target:
Bursting is disallowed, and no wait-states are gen-
erated. Target disconnects with data on first data word. The
FPGA portion of the device is not involved in configuration
transactions.
Master:
Single and burst operations are allowed.
Fully implemented.
Target:
Bursting is disallowed, and no wait-states are gen-
erated. Target disconnects with data on first data word. The
FPGA portion of the device is not involved in configuration
transactions.
Master:
Single and burst operations are allowed.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory read (4’b0110); the
user’s FPGA logic is responsible for ensuring that the Mas-
ter operation meets the special requirement that the read
request ends on a cacheline boundary.
Fully implemented. Per PCI Specification 2.1, Section
3.10.1, the PCI bus core (as a Master) automatically con-
verts a 64-bit address to a 32-bit address if the upper
32 bits are all zeros.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory read (0110). The user’s
FPGA logic is responsible for ensuring that the Master
operation meets the special requirement that the read
request continues to the next cacheline boundary.
Fully implemented. Both the Master and the Target treat this
instruction the same as a memory write (0111); the user’s
FPGA logic is responsible for ensuring that the Master
operation meets the special requirement that writes of com-
plete cachelines, with all byte enables, are performed.
1000
1001
1010
(reserved)
(reserved)
Configuration
Read
—
—
√
—
—
√
1011
Configuration
Write
√
√
1100
Memory Read
Multiple
√
√
1101
Dual-Access
Cycle
√
√
1110
Memory Read
Line
√
√
1111
Memory Write
and Invalidate
√
√
Command
Code
(Binary)
Command
OR3TP12
Master
Generates
OR3TP12
Target
Accepts
Description
PCI Bus Core Detailed Description
(continued)
Table 3. PCI Bus Command Descriptions
(continued)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR3TP12-6BA352 | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE |
| OR3TP12-6BA352I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE |
| OR3TP12-6PS240 | Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R |
| OR3TP12-6PS240I | Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R |
| OR3TP12 | Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR3TP126BA256I-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BA352-DB | 功能描述:FPGA - 現(xiàn)場(chǎng)可編程門陣列 2016 LUT 187 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR3TP12-6BA352I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:User Programmable Special Function ASIC |
| OR3TP126BAN256-DB | 制造商:Lattice Semiconductor Corporation 功能描述: |
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