參數(shù)資料
型號: OR3TP12-6BA256I
英文描述: Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, TUBE
中文描述: 用戶可編程ASIC的特殊功能
文件頁數(shù): 33/128頁
文件大?。?/td> 2450K
代理商: OR3TP12-6BA256I
Lucent Technologies Inc.
Lucent Technologies Inc.
33
Data Sheet
March 2000
ORCA OR3TP12 FPSC
Embedded Master/Target PCI Interface
PCI Bus Core Detailed Description
(continued)
Embedded Core/FPGA FIFO Interface Operation Summary
The following sections describe the Master and Target FIFO interface operation between the PCI bus core and the
FPGA application. Table 9 is an index to the state tables and timing figures provided for each of the operational
modes (dual-port, quad-port) of the FIFO interface.
Table 9. Index to State Sequence Tables
* The FPGA interface does not participate in Target configuration operations.
Dual-Port Mode
Quad-Port Mode
Master/
Target
PCI
Access
Type
Address
Type
Single/Burst and
Delayed/
Nondelayed
PCI
Bus
Timing
Figure
5
8
11
14
15
16
State
Table
FPGA
Bus
Timing
Figure
3
6
9
12
*
18
State
Table
FPGA
Bus
Timing
Figure
4
7
10
13
*
19
Master
Write
Config,
Memory, I/O
Config,
Memory, I/O
Config
I/O
Single
Burst
Single
Burst
Single
13
14
Read
15
16
17
21
Target
Write
20
Single, Delayed
Single,
Nondelayed
Single
Burst
Single
Delayed
Nondelayed
Single
Single, Delayed
Burst
Burst, Delayed
Memory
17
20
23
24
25
29
26
33
30
21
*
27
22
*
28
Read
Config
I/O
22
23
Memory
31
32
相關(guān)PDF資料
PDF描述
OR3TP12-6BA352 Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-PDIP, TUBE
OR3TP12-6BA352I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-TSSOP, TUBE
OR3TP12-6PS240 Single 2.3V 10 MHZ OP, -40C to +125C, 14-SOIC 150mil, T/R
OR3TP12-6PS240I Quad 2.3V 10 MHz OP, I temp, -40C to +85C, 14-SOIC 150mil, T/R
OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
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