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參數(shù)資料
| 型號： | MT93L04AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 128-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA365 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, BGA-365 |
| 文件頁數(shù)： | 47/56頁 |
| 文件大小： | 903K |
| 代理商： | MT93L04AG2 |
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MT93L04
Data Sheet
47
Zarlink Semiconductor Inc.
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
4:0
I<4:0>
I<4:0> binary code indicates the channel number at which a Tone Detector state
change has occurred.
Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Bit
Name
Description
7:1
res
Reserved bits. Must always be set to zero for normal operation.
0
Tirq
Test IRQ: Useful for the application engineer to verify the interrupt service routine.
When high, any change to MTDBI and MTDAI bits of the Main Control Register will
cause an interrupt and its corresponding channel number will be available from the
Interrupt FIFO Register.
When low, normal operation is selected.
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
1
I/O Supply Voltage (V
DD1
)
Core Supply Voltage (V
DD2
)
Input on any I/O pins
(other than supply pins)
V
DD1
-0.3
5.0
V
2
V
DD2
-0.3
2.5
V
3
V
I3
V
SS
- 0.3
V
DD1
+0.5
V
4
Input on any 5 V Tolerant I/O pins
V
I5
V
SS
- 0.3
5.5
V
5
Continuous Current at digital outputs
I
o
20
mA
6
Package power dissipation
P
D
2.0
W
7
Storage temperature
T
S
-55
150
°
C
Bit
Name
Description
Interrupt FIFO Register
I0
I1
I2
I3
I4
0
0
IRQ
7
6
5
4
3
2
1
0
Reset Value:
00
H
.
Read Address:
410
H
(Read only)
Test Register
Tirq
res
res
res
res
res
res
res
7
6
5
4
3
2
1
0
Reset Value:
00
H
.
Read/Write Address: 411
H
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