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參數(shù)資料
| 型號： | MT93L04AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 128-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA365 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, BGA-365 |
| 文件頁數(shù)： | 33/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | MT93L04AG2 |
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MT93L04
Data Sheet
33
Zarlink Semiconductor Inc.
The typical power consumption can be calculated with the following equation:
PC =9* Nb_of_groups + 3.6, in mW
where 0
<
Nb_of_groups
<
16
Call Initialization
To ensure fast initial convergence on a new call, it is important to clear the Adaptive filter. This is done by putting the
echo canceller in bypass mode for at least one frame (125
μ
s) and then enabling adaptation.
Interrupts
The MT93L00 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone
Disable is detected and released.
Although the MT93L00 may be configured to react automatically to tone disable status on any input PCM voice
channels, the user may want for the external HOST processor to respond to Tone Disable information in an
appropriate, application specific manner.
Each echo canceller will generate an interrupt when a Tone Disable occurs and will generate another interrupt
when a Tone Disable releases.
Upon receiving an IRQ, the HOST CPU should read the Interrupt FIFO Register. This register is a FIFO memory
containing the channel number of the echo canceller that has generated the interrupt.
All pending interrupts from any of the echo cancellers and their associated input channel number are stored in this
FIFO memory. The IRQ always returns high after a read access to the Interrupt FIFO Register. The IRQ pin will
toggle low for each pending interrupt.
After the HOST CPU has received the channel number of the interrupt source, the corresponding per channel
Status Register can be read from internal memory to determine the cause of the interrupt (see Figure 7 for address
mapping of Status register). The TD bit indicates the presence of a Tone Disable.
The MIRQ bit 5 in the Main Control Register 0 masks interrupts from the MT93L00. To provide more flexibility, the
MTDBI (bit-4) and MTDAI (bit-3) bits in the Main Control Register<15:0> allow Tone Disable to be masked or
unmasked, from generating an interrupt on a per channel basis. Refer to the Registers Description section.
JTAG Support
The MT93L00 JTAG interface conforms to the Boundary-Scan standard IEEE1149.1. This standard specifies a
design-for-testability technique called Boundary-Scan test (BST). The operation of the Boundary Scan circuitry is
controlled by an external Test Access Port (TAP) controller. JTAG inputs are 3.3 Volts compliant only.
Test Access Port (TAP)
The TAP provides access to many test functions of the MT93L00. It consists of three input pins and one output pin.
The following pins are found on the TAP.
Test Clock Input (TCK)
The TCK provides the clock for the test logic. The TCK does not interfere with any on-chip clock and thus remains
independent. The TCK permits shifting of test data into or out of the Boundary-Scan register cells concurrent with
the operation of the device and without interfering with the on-chip logic.
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