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參數(shù)資料
| 型號： | MT93L04AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 128-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA365 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, BGA-365 |
| 文件頁數(shù)： | 35/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | MT93L04AG2 |
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MT93L04
Data Sheet
35
Zarlink Semiconductor Inc.
Register Descriptions
Bit
Name
Description
7
Reset
When high, the power-up initialization is executed which presets all register bits
including this bit and clears the Adaptive Filter coefficients.
6
INJDis
When high, the noise injection process is disabled. When low noise injection is
enabled.
5
BBM
When high the Back to Back configuration is enabled.
When low the Normal configuration is enabled.
Note: Do not enable Extended-Delay and BBM configurations at the same time.
Always set
both
BBM bits of the two echo cancellers (Control Register A1 and
Control Register B1) of the same group to the same logic value to avoid conflict.
4
PAD
When high, 12 dB of attenuation is inserted into the Rin to Rout path.
When low the Rin to Rout path gain is 0 dB.
3
Bypass
When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout. The
Adaptive Filter coefficients are set to zero and the filter adaptation is stopped.
When low, output data on both Sout and Rout is a function of the echo canceller
algorithm.
2
AdpDis
When high, echo canceller adaptation is disabled. The MT93L00 cancels echo.
When low, the echo canceller dynamically adapts to the echo path characteristics.
1
0 or 1
Bits marked as “1” or “0” are reserved bits and should be written as indicated.
0
ExtDl
or
0
When high, Echo Cancellers A and B of the same group are internally cascaded into
one 128 ms echo canceller.
When low, Echo Cancellers A and B of the same group operate independently.
Note: Do not enable both Extended-Delay and BBM configurations at the same time.
Control Register B1 bit-0 is a reserved bit and should be written “0”.
Echo Canceller A, Control Register A1
Read/Write Address: 00
H
+ Base Address
0
AdpDis
Bypass
PAD
BBM
INJDis
Reset
7
6
5
4
3
2
1
0
ExtDl
Echo Canceller B, Control Register B1
Read/Write Address: 20
H
+ Base Address
1
AdpDis
Bypass
PAD
BBM
INJDis
Reset
7
6
5
4
3
2
1
0
0
Reset Value:
00
H
.
Reset Value:
02
H
.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT93L16 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:AEC with Noise Reduction & Codecs for Digital Hands-Free Communication |
| MT93L16AF | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.711 W/OUT TONE DETECTION 48TQFP - Rail/Tube |
| MT93L16AQ | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Low-Voltage Acoustic Echo Canceller |
| MT93L16AQ1 | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.711 W/OUT TONE DETECTION 36QSOP - Rail/Tube 制造商:Microsemi Corporation 功能描述:PB FREE LOW VOLT ACOUSTIC ECHO CANCELLER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC ECHO CANCEL ACOUSTIC 36SSOP 制造商:Microsemi Corporation 功能描述:IC ECHO CANCEL ACOUSTIC 36SSOP |
| MT94030049 MOD | 制造商:3M Electronic Products Division 功能描述:MOLD TECH ASSY |
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