- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359677 > MT93L04AG2 (ZARLINK SEMICONDUCTOR INC) 128-Channel Voice Echo Canceller PDF資料下載
參數(shù)資料
| 型號： | MT93L04AG2 |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 128-Channel Voice Echo Canceller |
| 中文描述： | DATACOM, ISDN ECHO CANCELLER, PBGA365 |
| 封裝： | 27 X 27 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, BGA-365 |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 903K |
| 代理商： | MT93L04AG2 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁
MT93L04
Data Sheet
13
Zarlink Semiconductor Inc.
TDI_d3
Signal
V13
Test Serial Data In (3.3 V Input).
JTAG serial test
instructions and data are shifted in on this pin.
This pin is pulled high by an internal pull-up when
not driven.
TDO_d3
Signal
Y14
Test Serial Data Out (Output).
JTAG serial data
is output on this pin on the falling edge of TCK.
This pin is held in high impedance state when
JTAG scan is not enabled.
TCK_d3
Signal
W14
Test Clock (3.3 V Input).
Provides the clock to
the JTAG test logic.
TRSTB_d3
Signal
Y15
Test Reset (3.3 V Input).
Asynchronously
initializes the JTAG TAP controller by putting it in
the Test-Logic-Reset state. This pin should be
pulsed low on power-up or held low, to ensure that
the MT93L00 is in the normal functional mode.
This pin is pulled by an internal pull-down when
not driven.
Test_En_d3
ICO
V14
Internal Connection.
Connected to VSS for
normal operation
RESETB_d3
Signal
W15
Device Reset (Schmitt Trigger Input).
An active
low resets the device and puts the MT93L00 into a
low-power stand-by mode.
When the RESET pin is returned to logic high
and a clock is applied to the MCLK pin, the
device will automatically execute initialization
routines, which preset all the Control and Status
Registers to their default power-up values.
IRQB_d3
Signal
Y16
Interrupt Request (Open Drain Output).
This
output goes low when an interrupt occurs in any
channel. IRQ returns high when all the interrupts
have been read from the Interrupt FIFO Register.
A pull-up resistor (1 K typical) is required at this
output.
DSB_d3
Signal
Y17
Data Strobe (Input).
This active low input works
in conjunction with CS to enable the read and
write operations.
CSB_d3
Signal
W16
Chip Select (Input).
This active low input is used
by a microprocessor to activate the
microprocessor port.
R/WB_d3
Signal
V15
Read/Write (Input).
This input controls the
direction of the data bus lines (D7-D0) during a
microprocessor access.
B_d3
Signal
Y18
Data Transfer Acknowledgment (Open Drain
Output).
This active low output indicates that a
data bus transfer is completed. A pull-up resistor
(1 K typical) is required at this output.
Pin Description (continued)
Signal Name
Signal Type
BGA Ball #
Signal Description
相關PDF資料 |
PDF描述 |
|---|---|
| MT93L00AB | Multi-Channel Voice Echo Canceller |
| MT93L00AV | Multi-Channel Voice Echo Canceller |
| MT91L60ASR | 3 Volt Multi-Featured Codec (MFC) |
| MT91L61ASR | 3 Volt Multi-Featured Codec (MFC) |
| MT91L61ASR1 | 3 Volt Multi-Featured Codec (MFC) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT93L16 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:AEC with Noise Reduction & Codecs for Digital Hands-Free Communication |
| MT93L16AF | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.711 W/OUT TONE DETECTION 48TQFP - Rail/Tube |
| MT93L16AQ | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:CMOS Low-Voltage Acoustic Echo Canceller |
| MT93L16AQ1 | 制造商:Microsemi Corporation 功能描述:ECHO CANCELLER CHIP 2CH G.711 W/OUT TONE DETECTION 36QSOP - Rail/Tube 制造商:Microsemi Corporation 功能描述:PB FREE LOW VOLT ACOUSTIC ECHO CANCELLER 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC ECHO CANCEL ACOUSTIC 36SSOP 制造商:Microsemi Corporation 功能描述:IC ECHO CANCEL ACOUSTIC 36SSOP |
| MT94030049 MOD | 制造商:3M Electronic Products Division 功能描述:MOLD TECH ASSY |
發(fā)布緊急采購，3分鐘左右您將得到回復。