參數(shù)資料
型號(hào)： MT93L04AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： 128-Channel Voice Echo Canceller
中文描述： DATACOM, ISDN ECHO CANCELLER, PBGA365
封裝： 27 X 27 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, BGA-365
文件頁(yè)數(shù)： 21/56頁(yè)
文件大?。?/td> 903K
代理商： MT93L04AG2
MT93L04
Data Sheet
21
Zarlink Semiconductor Inc.
Fsel_d4
Signal
A11
Frequency select (Input).
This input selects the
Master Clock frequency operation. When Fsel pin
is low, nominal 19.2 MHz Master Clock input must
be applied. When Fsel pin is high, nominal
9.6 MHz Master Clock input must be applied.
Halt_d4
ICO
E13
Internal Connection.
Connected to VSS for
normal operation
Step_d4
ICO
D14
Internal Connection.
Connected to VSS for
normal operation
PLLVSS1_d4
Power
E14
PLL Ground.
Must be connected to VSS
PLLVDD_d4
Power
D15
PLL Power Supply.
Must be connected to VDD2
PLLVSS2_d4
Power
D16
PLL Ground.
Must be connected to VSS
AT1_d4
NC
E15
No connection.
The pin must be left open for
normal operation.
Pin Description (continued)
Signal Name
Signal Type
BGA Ball #
Signal Description
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