參數(shù)資料
型號(hào)： MT93L04AG2
廠商： ZARLINK SEMICONDUCTOR INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： 128-Channel Voice Echo Canceller
中文描述： DATACOM, ISDN ECHO CANCELLER, PBGA365
封裝： 27 X 27 MM, 2.33 MM HEIGHT, LEAD FREE, MS-034, BGA-365
文件頁(yè)數(shù)： 38/56頁(yè)
文件大?。?/td> 903K
代理商： MT93L04AG2
MT93L04
Data Sheet
38
Zarlink Semiconductor Inc.
The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS
adaptation step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the
performance of the echo canceller to be optimized for specific applications. For example, if the characteristic of the
echo response is known to have a flat delay of several milliseconds and a roughly exponential decay of the echo
impulse response, then the MU profile can be programmed to approximate this expected impulse response thereby
improving the convergence characteristics of the Adaptive Filter. Note that in the following register descriptions, one
tap is equivalent to 125
μ
s (64 ms/512 taps).
FD7
FD6
FD5
FD4
FD2
FD1
FD0
FD3
Power Reset Value
00h
7
6
5
4
3
2
1
0
Echo Canceller A, Flat Delay Register (FD)
Echo Canceller B, Flat Delay Register (FD)
Read/Write Address:
04h
+ Base Address
Read/Write Address:
24h
+ Base Address
Power Reset Value
00h
7
6
5
4
3
2
1
0
NS7
NS6
NS5
NS4
NS2
NS1
NS0
NS3
Echo Canceller A, Decay Step Number Register (NS)
Echo Canceller B, Decay Step Number Register (NS)
Read/Write Address:
07h
+ Base Address
Read/Write Address:
27h
+ Base Address
Power Reset Value
04h
7
6
5
4
3
2
1
0
0
0
0
0
SSC2
SSC1
SSC0
0
Echo Canceller A, Decay Step Size Control Register (SSC)
Echo Canceller B, Decay Step Size Control Register (SSC)
Read/Write Address:
06h
+ Base Address
Read/Write Address:
26h
+ Base Address
Note: Bits marked with “0” are reserved bits and should be written “0”.
Amplitude of MU
Time
Flat Delay (FD
7-0
)
Step Size (SS)
1.0
2-16
FIR Filter Length (512 or 1024 taps)
Number of Steps (NS
7-0
)
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