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2-6
MPC7400 RISC Microprocessor Users Manual
The MPC7400 Processor Register Set
Note that setting MSR[EE] masks not only the architecture-deTned external
interrupt and decrementer exceptions but also the MPC7400-speciTc system
management, performance monitor, and thermal management exceptions.
D Processor version register (PVR). This register is a read-only register that
identiTes the version (model) and revision level of the PowerPC processor.
For more information, see òProcessor Version Register (PVR),ó in Chapter 2,
òPowerPC Register Set,ó of
The Programming Environments Manual
.
Implementation Note
The processor version number is 0x0008 for the
MPC7400. The processor revision level starts at 0x0100 and is updated for
each silicon revision.
D Processor ID register. Implemented as deTned in the OEA.
Memory management registers
D Block-address translation (BAT) registers. The PowerPC OEA includes an
array of block address translation registers that can be used to specify four
blocks of instruction space and four blocks of data space. The BAT registers
are implemented in pairsfour pairs of instruction BATs (IBAT0UDIBAT3U
and IBAT0LDIBAT3L) and four pairs of data BATs (DBAT0UDDBAT3U and
DBAT0LDDBAT3L). Figure 2-1 lists the SPR numbers for the BAT registers.
For more information, see òBAT Registers,ó in Chapter 2, òPowerPC Register
Set,ó of
The Programming Environments Manual
. Because BAT upper and
lower words are loaded separately, software must ensure that BAT translations
are correct during the time that both BAT entries are being loaded.
The MPC7400 implements the G bit in the IBAT registers; however,
attempting to execute code from an IBAT area with G = 1 causes an ISI
Table 2-1. Additional MSR Bits
Bits
Name
Description
6
VEC
AltiVec available. The AltiVec technology is optional to the PowerPC architecture.
0 AltiVec technology is disabled.
1 AltiVec technology is enabled.
Note: Any attempt to execute a non-stream AltiVec instruction when the bit is cleared causes the
processor to execute an òAltiVec Unavailable Exceptionó when the instruction accesses the vector
register Tle (VRF) or VSCR register. This exception does not happen for data streaming instructions
(
dst(t)
,
dstst(t)
, and
dss
), that is, the VRF and VSCR registers are available to the data streaming
instructions even when the MSR[VEC] is cleared.
The VRSAVE register is not protected by MSR [VEC], that is, it can be accessed
even when MSR[VEC] is cleared.
13
POW
Power management enable. Optional to the PowerPC architecture.
0 Power management is disabled.
1 Power management is enabled. The processor can enter a power-saving mode when additional
conditions are present. The mode chosen is determined by the DOZE, NAP, and SLEEP bits in
the hardware implementation-dependent register 0 (HID0), described in Table 2-4.
29
PM
Performance monitor marked mode. This bit is speciTc to the MPC7400, and is deTned as reserved
by the PowerPC architecture. See Chapter 11, òPerformance Monitor.ó
0 Process is not a marked process.
1 Process is a marked process for the performance monitor.