2-12
MPC7400 RISC Microprocessor Users Manual
The MPC7400 Processor Register Set
6
ECLK
CLK_OUT output enable and clock type selection. Used in conjunction with HID0[BCLK] and
the HRESET signal to conTgure CLK_OUT. See Table 2-5.
7
PAR
Disable precharge of ARTRY and SHD[0] or SHD[1].
0 Precharge of ARTRY enabled
1 Alters bus protocol slightly by preventing the processor from driving ARTRY to high
(negated) state. If this is done, the system must restore the signals to the high state.
8
DOZE
Doze mode enable. Operates in conjunction with MSR[POW].
0 Doze mode disabled.
1 Doze mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is set. In
doze mode, the PLL, time base, and snooping remain active.
9
NAP
Nap mode enable. Operates in conjunction with MSR[POW].
0 Nap mode disabled.
1 Nap mode enabled. Doze mode is invoked by setting MSR[POW] while this bit is set. In nap
mode, the PLL and the time base remain active.
10
SLEEP
Sleep mode enable. Operates in conjunction with MSR[POW].
0 Sleep mode disabled.
1 Sleep mode enabled. Sleep mode is invoked by setting MSR[POW] while this bit is set.
QREQ is asserted to indicate that the processor is ready to enter sleep mode. If the system
logic determines that the processor can enter sleep mode, the quiesce acknowledge signal,
QACK, is asserted back to the processor. When the QACK signal assertion is detected, the
processor enters sleep mode after several processor clocks. At this point, the system logic
can turn off the PLL by Trst conTguring PLL_CFG[0:3] to PLL bypass mode, then disabling
SYSCLK.
11
DPM
Dynamic power management enable.
0 Dynamic power management is disabled.
1 Functional units enter a low-power mode automatically if the unit is idle. This does not affect
operational performance and is transparent to software or any external hardware.
12
RISEG
Read I SEG (test only).
0 Data segreg services
mfsr
.
1 Instruction segreg services
mfsr
.
See Section 2.3.6.3.2, òSegment Register Manipulation Instructions (OEA).ó
13
EIEC
Enable internal error checking.
0 Errors disabled.
1 Error enabled for DCERR, ICERR, L2ERR, BRERR, TLBERR, and OTHERR errors. The
processor will only take checkstop and machine check action for these error if EIEC is set
14
Reserved.
15
NHR
Not hard reset (software-use only)Helps software distinguish a hard reset from a soft reset.
0 A hard reset occurred if software had previously set this bit.
1 A hard reset has not occurred. If software sets this bit after a hard reset, when a reset occurs
and this bit remains set, software can tell it was a soft reset.
The MPC7400 never writes this bit unless executing an
mtspr
(HID0).
16
ICE
Instruction cache enable.
0 The instruction cache is neither accessed nor updated. All pages are accessed as if they
were marked cache-inhibited (WIM = x1x). Potential cache accesses from the bus (snoop
and cache operations) are ignored. In the disabled state for the L1 caches, the cache tag
state bits are ignored and all accesses are propagated to the L2 cache or bus as single-beat
transactions. For those transactions, CI is asserted regardless of address translation. ICE is
zero at power-up.
1 The instruction cache is enabled.
Table 2-4. HID0 Field Descriptions (Continued)
Bits
Name
Function