![](http://datasheet.mmic.net.cn/270000/MPC7400_datasheet_16037847/MPC7400_193.png)
Chapter 3. L1 and L2 Cache Operation
3-15
Memory and Cache Coherency
Note that when SHDEN = 0b0, the MPC7400 snoops read transactions as if they were
RWITM transactions. Also when SHDEN = 0b0, any MPC7400-initiated read transaction
that generates a SHD-assertion response is treated as an invalidate operation.
In the following state transition diagrams, RWNITC is not explicitly shown. For state
transitions (for example, modiTed to exclusive) RWNITC is treated like a clean operation.
For intervention purposes (for example a W or H intervention) RWNITC is treated like a
read operation.
3.4.3.4 MESI State Transitions
In the following state transition diagrams, all snooped transactions are assumed to be global
(GBL asserted), caching-allowed (CI negated), and write-back (WT negated). If either CI
or WT is asserted, then the state transitions remain the same, but no data intervention
occurs. Instead, a window-of-opportunity snoop push is performed only for snoop hits to
modiTed cache blocks.
The state diagrams use symbols on the transistion lines for snoop response and intervention
type. For example, H1S-CW would denote a one-cycle HIT and SHD asserted snoop
Table 3-7. Simplified Transaction Types
SimpliTed Transaction
Type
Actual Transaction Type
MESI or MERSI Protocol
(SHDEN = 1)
Actual Transaction Type
MEI Protocol
(SHDEN = 0)
Read
Read
Read-atomic
RWITM
RWITM
RWITM-atomic
RCLAIM
Read
Read-atomic
RWITM
RWITM-atomic
RCLAIM
RWNITC
RWNITCActs like a read transaction for
snoop response purposes; acts like a clean
transaction for MESI state change
purposes.
RWNITCActs like a RWITM transaction
for snoop response purposes; acts like a
clean transaction for MEI state change
purposes.
Write
Write-with-ush
Write-with-ush-atomic
Flush
Flush
Clean
Clean
Kill
Kill
Write-with-kill
Reskill
(Used for reservation
snooping only)
RWITM
RWITM-atomic
RCLAIM
Write-with-ush
Write-with-ush-atomic
Kill
Write-with-kill