參數(shù)資料
型號： ML60851DTB
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁數(shù)： 77/84頁
文件大?。?/td> 394K
代理商： ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
78/83
(2) 2-Layer transmission operation (O indicates the assert (set to “1”) condition and X indicates de-assert (set to
“0”) condition)
In the case of 1
→2→3→4→5a→6
In the case of 1
→2→3→4→5b→6
Layer A
64 bytes
Layer B
64 bytes
Layer A
PKT
RDY
Layer B
PKT
RDY
EP1
transmit
PKT
RDY
INTR
1
Layer A and layer B are both empty.
××
×
2
The local MCU starts writing into layer A.
××
×
3
Writing of one packet is completed.
××
4
Data of layer A is being transmitted while
the next packet is being written in layer B.
××
5a
When layer A is still being transmitted
while writing in layer B is completed.
×
5b
When layer B is still being written while
layer A has already become empty.
××
×
6
From 5a: Layer A has become empty.
From 5b: Layer B has become full.
××
7
Transmission of layer B is also started.
××
If the EP1 transmit packet ready interrupt enable bit has been asserted, the transmit FIFO is empty, and EP1
transmit packet ready bit is de-asserted, the EP1 transmit packet ready interrupt is asserted. This makes it
possible to write the transmit data into the EP1 transmit FIFO.
When the data of one packet is written in layer A FIFO, make the local MCU set the transmit packet ready status
(D5 of PKTRDY set to “1”). By setting the transmit packet ready status, it becomes possible to transmit data to
the host. At this time, since layer B is still empty, the
INTR pin maintains the asserted condition, thereby
indicating that the next packet data can be written. In this case, although bit D5 of PKTRDY remains in the “0”
condition, the ML60851D recognizes that transmission is possible from layer A and starts transmission when an
IN token is received from the host.
It is possible for the local MCU to write the next packet of transmit data in the layer B FIFO while the data in
layer A is being transmitted over the USB bus.
When the writing of the data to be transmitted in layer B has been completed, the local MCU sets the transmit
packet ready bit, and the
INTR pin becomes de-asserted at this time if the transmission of layer A data has not
been completed (that is, the ACK message is received from the host and the transmit packet ready bit is reset).
The local MCU cannot yet write the subsequent packet.
If the layer A becomes empty before layer B goes into the transmit enable condition and transmission is carried
out normally, an ACK response is received from the host. The
INTR pin remains asserted, and the local MCU
can write data into layer A FIFO after writing into layer B FIFO.
The transmission of data in layer A is continued from the state 4a, and when layer A becomes empty and the
transmission is completed normally, an ACK response is received from the host, whereupon the ML60851D
asserts the
INTR pin thereby prompting the local MCU to write data into layer A.
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