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參數(shù)資料
| 型號： | ML60851DTB |
| 廠商： | LAPIS SEMICONDUCTOR CO LTD |
| 元件分類： | 總線控制器 |
| 英文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP44 |
| 封裝： | 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44 |
| 文件頁數(shù)： | 24/84頁 |
| 文件大?。?/td> | 394K |
| 代理商： | ML60851DTB |
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FEDL60851D-01
1Semiconductor
ML60851D
29/83
During data reception, the packet ready interrupt is generated when one
packet of receive data is correctly stored in one of the two FIFO layers of
EP1. During transmission, the packet ready interrupt is generated when data
transmission has been completed from (and writing becomes possible again)
one of the two FIFO layers of EP1.
EP2 Packet Ready Interrupt Status: When bit D2 of the interrupt enable register (INTENBL) is “0” (ednpoint 2
interrupt is masked), the content of this bit is “0” and hence no interrupt is
generated.
When endpoint 2 is configured as a receive endpoint (EP2CON D7=0), if bit
D2 of the interrupt enable register (INTENBL) is “1” (EP2 interrupt enabled),
the content of bit D2 of the endpoint packet ready register (PKTRDY) is
copied here.
When endpoint 2 is configured as a transmit endpoint (EP2CON D7=1), if
bit D2 of the interrupt enable register (INTENBL) is “1” (EP2 interrupt
enabled), the inverted (logical NOT) content of bit D6 of the endpoint pakcet
ready register (PKTRDY) is copied here.
In other words, when endpoint 2 packet ready interrupt (D2 of INTENBL)
has been set to “1” the following statements become true:
During data reception, the packet ready interrupt is generated when one
packet of receive data is correctly stored in the FIFO of EP2.
During
transmission, the packet ready interrupt is generated when data transmission
has been completed from (and writing becomes possible again) the FIFO of
EP2.
EP0 Receive Packet Ready Interrupt Status:
When bit D3 of the interrupt enable register (INTENBL) is “1”, the content
of bit D0 of the end point packet ready register (PKTRDY) is copied here.
This bit is “0” when bit D3 of INTENBL is “0”.
In other words, when endpoint 0 receive packet ready interrtup (D3 of
INTENBL) has been enabled, if a data packet is received in the data stage of
control transfer and is correctly stored in the EP0RXFIFO, this bit is set to
“1” and the
INTR pin is asserted.
EP0 Transmit Packet Ready Interrupt Status:
When bit D4 of the interrupt enable register (INTENBL) is “1”, the inverted
(logical NOT) content of bit D4 of the end point packet ready register
(PKTRDY) is copied here. This bit is “0” when bit D4 of INTENBL is “0”.
In other words, when endpoint 0 transmit packet ready interrupt (D4 of
INTENBL) has been enabled (set to “1”), if the transmission from
EP0TXFIFO is completed, an ACK is received from the host in response to
the succussful transmission which will inturn cause the ML60851D to
automatically deassert (set to “0”) its EP0 transmit packet ready bit (D4 of
PKTRDY) and inturn set this bit and hence generate an interrupt.
The value at the time of a bus reset is based on the value of D4 of INTENBL
just prior to bus reset. If D4 of INTENBL was “1” prior to reset, its value will
be the same during a bus reset and hence this bit will be “1” and an interrupt
will be generated. If D4 of INTENBL was “0” prior to bus reset, interrupt for
endpoint 0 was disabled and hence the value of this bit will be “0” after a bus
reset.
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相關代理商/技術參數(shù) |
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| ML60851E | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60851EGA | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60851ETB | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
| ML60852A | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:USB Device Controller |
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