參數(shù)資料
型號(hào)： ML60851DTB
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁(yè)數(shù)： 39/84頁(yè)
文件大?。?/td> 394K
代理商： ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
43/83
End Point 3 Control Register (EP3CON)
Read address
F8h
Write address
78h
D7
D6
D5
D4
D3
D2
D1
D0
After a hardware reset
0
1
x
0
After a bus reset
001
111
x
0
Definition
01
111
Configuration Bit:
The local MCU should write a “1” in this bit during the status stage of control transfer
when a “Set Configuration” request is received from the host computer to make EP3
active.
When this bit is “1”, the exchange of data between the host computer and EP3 is
enabled. When this bit is “0”, this IC does not respond to any transactions with this
EP.
Stall Bit:
When this bit is “1”, the stall handshake is automatically returned to the host computer
in response to the packet transmitted to the host computer from this end point.
The EP3 transfer mode is set as an interrupt transfer and the end point address is fixed at 3h. Therefore, the bits D6
to D2 have fixed values, and other values written in them are invalid.
Toggling Condition Bit:
When this bit is “0”, toggling is performed between DATA0 and DATA1 every time
an ACK is sent from the host computer to EP3.
If this bit is set to “1”, the rate feedback mode will be set. In this case, the toggling is
performed every time the packet ready bit is asserted.
Configuration Bit (R/W)
Stall Bit (R/W)
Transfer Type (R)
11b = Interrupt Transfer
End Point Address
Toggling Condition (R/W)
0 = Normal
1 = Rate feedback mode
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