參數(shù)資料
型號(hào)： ML60851DTB
廠商： LAPIS SEMICONDUCTOR CO LTD
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PQFP44
封裝： 10 X 10 MM, 0.80 MM PITCH, PLASTIC, TQFP-44
文件頁數(shù)： 69/84頁
文件大?。?/td> 394K
代理商： ML60851DTB
FEDL60851D-01
1Semiconductor
ML60851D
70/83
(5) Transmit packet ready interrupts (EP1, EP2, EP3)
These interrupts are generated when it is possible for the local MCU to write the data packet to be sent to the
USB bus from the corresponding EP.
Operation
Source of operation
Description (conditions, responses, etc.)
Transmit packet ready
interrupt generation
ML60851D
(1) In the case of bulk transfer and interrupt transfer
When the respective EP has been set for transmission,
the transmit packet ready bit of the corresponding EP is
de-asserted when it is possible to write the transmit
data into the FIFO.
At this time, an interrupt is generated if the
corresponding EP transmit packet ready interrupt
enable bit (INTENBL) has been asserted.
For the second and subsequent packets, in addition to
this condition, before the interrupt is generated, it is
necessary for an ACK response to come from the host
for the packet that has just been sent.
End of transmit packet ready
interrupt
Local MCU (firmware)
(1) In the case of bulk transfer and interrupt transfer
After the one packet of the corresponding EP transmit
data has been written in EPnTXFIFO, write a “1” into
the corresponding transmit packet ready bit (PKTRDY
register). This puts the ML60851D in a state in which it
can transmit the data and the
INTR pin is de-asserted
at the same time.
When the number of bytes in the write data is less than
the maximum payload size of the endpoint, a short
packet can be transmitted by writing a “1” into the
transmit packet ready bit (PKTRDY register).
The following table outlines the relationship between ML60851D registers and packet ready interrupt generation
during a transmit (device to host communication) operation.
INTENBL(D1/D2/D7)*
EPnCON(D7)
I
Tx PKTRDY(D5/D6/D7)*
INTSTAT(D1/D2/D7)*
10
X
0
1110
1101
0X
X0
X This symbol means that it does not matter whether the value is ‘1’ or ‘0’
* Use the appropriate bit field corresponding to the endpoint being considered
I
EP3 is only capable of transmission and hence this register does not play a roll in interrupt generation of EP3
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