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| 型號： | M7A3PE600-FFGG256I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 600000 GATES, PBGA256 |
| 封裝： | 1 MM PITCH, GREEN, FBGA-256 |
| 文件頁數(shù)： | 99/168頁 |
| 文件大?。?/td> | 1335K |
| 代理商： | M7A3PE600-FFGG256I |
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ProASIC3E Flash Family FPGAs
2- 24
Advanced v0.5
Signal Descriptions for RAM4K9
The following signals are used to configure the RAM4K9
memory element:
WIDTHA and WIDTHB
These signals enable the RAM to be configured in one of
four allowable aspect ratios (Table 2-5).
BLKA and BLKB
These signals are active low and will enable the
respective ports when asserted. When a BLKx signal is
deasserted, that port’s outputs hold the previous value.
WENA and WENB
These signals switch the RAM between read and write
modes for the respective ports. A low on these signals
indicates a write operation, and a high indicates a read.
CLKA and CLKB
These are the clock signals for the synchronous read and
write operations. These can be driven independently or
with the same driver.
PIPEA and PIPEB
These signals are used to specify pipelined read on the
output. A low on PIPEA or PIPEB indicates a nonpipelined
read, and the data appears on the corresponding output
in the same clock cycle. A high indicates a pipelined read,
and data appears on the corresponding output in the
next clock cycle.
WMODEA and WMODEB
These signals are used to configure the behavior of the
output when RAM is in the write mode. A low on these
signals makes the output retain data from the previous
read. A high indicates pass-through behavior, wherein
the data being written will appear immediately on the
output. This signal is overridden when the RAM is being
read.
RESET
This active low signal resets the control logic and forces
the output hold state registers to zero when asserted. It
does not reset the contents of the memory array.
While the RESET signal is active, read and write
operations are disabled. As with any asynchronous reset
signal, care must be taken not to assert it too close to the
edges of active read and write clocks. Refer to the tables
beginning
with
for
the
specifications.
ADDRA and ADDRB
These are used as read or write addresses, and they are 12
bits wide. When a depth of less than 4 k is specified, the
unused high-order bits must be grounded (Table 2-6).
DINA and DINB
These are the input data signals, and they are nine bits
wide. Not all nine bits are valid in all configurations.
When a data width less than nine is specified, unused
high-order signals must be grounded (Table 2-7).
DOUTA and DOUTB
These are the nine-bit output data signals. Not all nine
bits are valid in all configurations. As with DINA and
DINB, high-order bits may not be used (Table 2-7). The
output data on unused pins is undefined.
Table 2-5 Allowable Aspect Ratio Settings for
WIDTHA[1:0]
WIDTHA[1:0]
WIDTHB[1:0]
DxW
00
4kx1
01
2kx2
10
1kx4
11
512x9
Note: The aspect ratio settings are constant and cannot be
changed on-the-fly.
Table 2-6 Address Pins Unused/Used for Various
Supported Bus Widths
DxW
ADDRx
Unused
Used
4kx1
None
[11:0]
2kx2
[11]
[10:0]
1kx4
[11:10]
[9:0]
512x9
[11:9]
[8:0]
Note: The "x" in ADDRx implies A or B.
Table 2-7 Unused/Used Input and Output Data Pins for
Various Supported Bus Widths
DxW
DINx/DOUTx
Unused
Used
4kx1
[8:1]
[0]
2kx2
[8:2]
[1:0]
1kx4
[8:4]
[3:0]
512x9
None
[8:0]
Note: The "x" in DINx or DOUTx implies A or B.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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