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| 型號(hào)： | M7A3PE600-FFGG256I |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 600000 GATES, PBGA256 |
| 封裝： | 1 MM PITCH, GREEN, FBGA-256 |
| 文件頁(yè)數(shù)： | 132/168頁(yè) |
| 文件大小： | 1335K |
| 代理商： | M7A3PE600-FFGG256I |
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ProASIC3E Flash Family FPGAs
2- 54
Advanced v0.5
can be implemented easily and securely by simply
sending a STAPL file with AES encrypted data. Secure
remote field updates over public networks (such as the
Internet) are possible by sending and programming a
STAPL file with AES encrypted data.
128-Bit AES Decryption
The 128-bit AES standard (FIPS-192) block cipher is the
NIST (National Institute of Standards and Technology)
replacement for the DES (Data Encryption Standard
FIPS46-2). AES has been designed to protect sensitive
government information well into the 21st century. It
replaces the aging DES, which NIST adopted in 1977 as a
Federal Information Processing Standard used by federal
agencies to protect sensitive, unclassified information.
The 128-bit AES standard has 3.4x1038 possible 128-bit
key variants, and it has been estimated that it would
take 1,000 trillion years to crack 128-bit AES cipher text
using exhaustive techniques. Keys are stored (securely) in
ProASIC3E devices in nonvolatile Flash memory. All
programming
files
sent
to
the
device
can
be
authenticated by the part prior to programming to
ensure that bad programming data is not loaded into
the part that may possibly damage it. All programming
verification is performed on-chip, ensuring that the
contents of ProASIC3E devices remain secure.
AES decryption can also be used on the 1,024-bit
FlashROM to allow for secure remote updates of the
FlashROM contents. This allows for easy, secure support
for subscription model products. See the application
note ProASIC3/E Security for more details.
ISP
ProASIC3E devices support IEEE 1532 ISP via JTAG and
require a single VPUMP voltage of 3.3 V during
programming.
In
addition,
programming
via
a
Microcontroller (MCU) in a target system can be
achieved.
See
the
application
note
more details.
JTAG 1532
ProASIC3E devices support the JTAG-based IEEE 1532
standard for ISP. As part of this support, when a ProASIC3E
device is in an unprogrammed state, all user I/O pins are
disabled. This is achieved by keeping the global IO_EN
signal deactivated, which also has the effect of disabling
the input buffers. The SAMPLE/PRELOAD instruction
captures the status of pads in parallel and shifts them out as
new data is shift in for loading into the Boundary Scan
Register.
When
the
ProASIC3E
device
is
in
an
unprogrammed state, the SAMPLE/PRELOAD instruction
has no effect on I/O status, however, it will continue to shift
in new data to be loaded into the BSR; therefore, when
SAMPLE/PRELOAD is used on an unprogrammed device, the
BSR will be loaded with undefined data. Refer to the In-
application note for more details.
For JTAG timing information of setup, hold, and fall times,
refer to the FlashPro User’s Guide.
Boundary Scan
ProASIC3E devices are compatible with IEEE Standard
1149.1, which defines a hardware architecture and the
set of mechanisms for boundary scan testing. The basic
ProASIC3E boundary scan logic circuit is composed of the
TAP (test access port) controller, test data registers, and
instruction register (Figure 2-37 on page 2-55). This
circuit supports all mandatory IEEE 1149.1 instructions
(EXTEST,
SAMPLE/PRELOAD,
and
BYPASS)
and
the
optional IDCODE instruction (Table 2-25 on page 2-55).
Each test section is accessed through the TAP, which has
five associated pins: TCK (test clock input), TDI, TDO (test
data input and output), TMS (test mode selector), and
TRST (test reset input). TMS, TDI, and TRST are equipped
with pull-up resistors to ensure proper operation when
no input data is supplied to them. These pins are
dedicated for boundary scan test usage. Refer to the
"JTAG Pins" section on page 2-52 for pull-up/down
recommendations for TDO and TCK pins. The TAP
controller is a 4-bit state machine (16 states) that
operates as shown in Figure 2-37 on page 2-55. The 1s
and 0s represent the values that must be present at TMS
at a rising edge of TCK for the given state transition to
occur. IR and DR indicate that the instruction register or
the data register is operating in that state.
The TAP controller receives two control inputs (TMS and
TCK) and generates control and clock signals for the rest
of the test logic architecture. On power-up, the TAP
controller enters the Test-Logic-Reset state. To guarantee
a reset of the controller from any of the possible states,
TMS must remain high for five TCK cycles. The TRST pin
may also be used to asynchronously place the TAP
controller in the Test-Logic-Reset state.
ProASIC3E devices support three types of test data
registers: bypass, device identification, and boundary
scan. The bypass register is selected when no other
register needs to be accessed in a device. This speeds up
test data transfer to other devices in a test data path.
The 32-bit device identification register is a shift register
with four fields (LSB, ID number, part number, and
version). The boundary scan register observes and
controls the state of each I/O pin. Each I/O cell has three
boundary scan register cells, each with a serial-in, serial-
out, parallel-in, and parallel-out pin.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M7A5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7A9 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M7AFS600-1FG256 | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
| M7AFS600-1FG256ES | 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:Actel Fusion Mixed-Signal FPGAs |
| M7AFS600-1FG256I | 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays |
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