參數(shù)資料
型號： M7A3PE600-FFGG256I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA256
封裝： 1 MM PITCH, GREEN, FBGA-256
文件頁數(shù)： 144/168頁
文件大?。?/td> 1335K
代理商： M7A3PE600-FFGG256I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-9
Combinational Cells Contribution—PC-CELL
PC-CELL = NC-CELL* α1/2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-11 on page 3-10.
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * α1/2 * PAC8 * FCLK
NS-CELL is the number VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
α
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 3-11 on page 3-10.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * α2/2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 3-11 on page 3-10.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * α2/2 * β1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
α
2 is the I/O buffer toggle rate—guidelines are provided in Table 3-11 on page 3-10.
β
1 is the I/O buffer enable rate—guidelines are provided in Table 3-12 on page 3-10.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3
NBLOCKS is the number RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
β
2 is the RAM enable rate for read operations—guidelines are provided in Table 3-12 on page 3-10.
FWRITE-CLOCK is the memory write clock frequency.
β
3 the RAM enable rate for write operations—guidelines are provided in Table 3-12 on page 3-10.
PLL/CCC contribution—PPLL
PPLL = PAC13 * FCLKIN + Σ PAC14 * FCLKOUT
FCLKIN is the input clock frequency.
FCLKOUT
1 is the output clock frequency.
1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula output clock by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL
contribution.
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