參數(shù)資料
型號： M7A3PE600-FFGG256I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA256
封裝： 1 MM PITCH, GREEN, FBGA-256
文件頁數(shù)： 140/168頁
文件大小： 1335K
代理商： M7A3PE600-FFGG256I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
3-5
Calculating Power Dissipation
Quiescent Supply Current
Power per I/O Pin
Table 3-7
Quiescent Supply Current Characteristics
A3PE600
A3PE1500
A3PE3000
Typical (25°C)
5 mA
12 mA
25 mA
Maximum (Commercial)
30 mA
70 mA
150 mA
Maximum (Industrial)
45 mA
105 mA
225 mA
Notes:
1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is shown in Table 3-8 and
2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher I/O leakage.
Table 3-8
Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
VMV
(V)
Static Power
PDC2 (mW)
1
Dynamic Power
PAC9 (W/MHz)
2
Single-Ended
3.3 V LVTTL/LVCMOS
3.3
–
17.39
3.3 V LVTTL/LVCMOS – Schmitt trigger
3.3
–
25.51
2.5 V LVCMOS
2.5
–
5.76
2.5 V LVCMOS – Schmitt trigger
2.5
–
7.16
1.8 V LVCMOS
1.8
–
2.72
1.8 V LVCMOS – Schmitt trigger
1.8
–
2.80
1.5 V LVCMOS (JESD8-11)
1.5
–
2.08
1.5 V LVCMOS (JESD8-11) – Schmitt trigger
1.5
–
2.00
3.3 V PCI
3.3
–
18.82
3.3 V PCI – Schmitt trigger
3.3
–
20.12
3.3 V PCI-X
3.3
–
18.82
3.3 V PCI-X – Schmitt trigger
3.3
–
20.12
Voltage-Referenced
3.3 V GTL
3.3
2.90
8.23
2.5 V GTL
2.5
2.13
4.78
3.3 V GTL +
3.3
2.81
4.14
2.5 V GTL +
2.5
2.57
3.71
HSTL (I)
1.5
0.17
2.03
HSTL (II)
1.5
0.17
2.03
SSTL2 (I)
2.5
1.38
4.48
SSTL2 (II)
2.5
1.38
4.48
SSTL3 (I)
3.3
3.21
9.26
SSTL3 (II)
3.3
3.21
9.26
Differential
LVDS/BLVDS/M-LVDS
2.5
2.26
1.50
LVPECL
3.3
5.71
2.17
Notes:
1. PDC2 is the static power (where applicable) measured on VMV.
2. PAC9 is the total dynamic power measured on VCC and VMV.
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