參數(shù)資料
型號： M7A3PE600-FFGG256I
元件分類： FPGA
英文描述： FPGA, 600000 GATES, PBGA256
封裝： 1 MM PITCH, GREEN, FBGA-256
文件頁數(shù)： 107/168頁
文件大小： 1335K
代理商： M7A3PE600-FFGG256I
ProASIC3E Flash Family FPGAs
A d v an c ed v0 . 5
2-31
Features Supported on Every I/O
Table 2-15 lists all features supported by transmitter/receiver for single-ended and differential I/Os.
Table 2-15 I/O Features ProASIC3E
Feature
Description
Single-Ended and Voltage-Referenced Transmitter Features
Hot insertion in every mode except PCI or 5 V input tolerant
(these modes use clamp diodes and do not allow hot insertion)
Activation of hot insertion (disabling the clamp diode) is
selectable by I/Os
Weak pull-up and pull-down
Two slew rates
Skew between output buffer enable/disable time: 2 ns delay
on the rising edge and 0 ns delay on the falling edge (see the
Time" section on page 2-43 for more information).
Five drive strengths
LVTTL/LVCMOS 3.3 V outputs compatible with 5 V TTL inputs
High Performance (Table 2-16 on page 2-32
)
Single-Ended Receiver Features
ESD protection
Schmitt Trigger option
Programmable Delay: 0 ns if bypassed, 0.46 ns with 000
setting, 4.66 ns with 111 setting, 0.6 ns intermediate delay
increments (at 25°C, 1.5 V)
High performance (Table 2-16 on page 2-32)
Separate ground plane for GNDQ pin and power plane for VMV
pin are used for input buffer to reduce output induced noise.
Voltage-Referenced Differential Receiver Features
Programmable Delay: 0 ns if bypassed, 0.46 ns with 000
setting, 4.66 ns with 111 setting, 0.6 ns intermediate delay
increments (at 25°C, 1.5 V)
High performance (Table 2-16 on page 2-32)
Separate ground plane for GNDQ pin and power plane for VMV
pin are used for input buffer to reduce output induced noise.
CMOS-Style LVDS, BLVDS, M-LVDS or LVPECL Transmitter
Two I/Os and external resistors are used to provide a CMOS-
style LVDS, DDR LVDS, BLVDS, and M-LVDS or LVPECL
transmitter solution.
Activation of hot insertion (disabling the clamp diode) is
selectable by I/Os.
Weak pull-up and pull-down
High slew rate
LVDS, DDR LVDS, BLVDS, and M-LVDS/LVPECL Differential Receiver
Features
ESD protection
High performance (Table 2-16 on page 2-32)
Programmable Delay: 0 ns if bypassed, 0.46 ns with 000
setting, 4.66 ns with 111 setting, 0.6 ns intermediate delay
increments (at 25°C, 1.5 V)
Separate input buffer ground and power planes to avoid
output-induced noise in the input circuitry
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相關代理商/技術參數(shù)
參數(shù)描述
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M7AFS600-1FG256 制造商:Microsemi Corporation 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays 制造商:Microsemi SOC Products Group 功能描述:FPGA FUSION 600K GATES 1282.05MHZ 130NM 1.5V 256FBGA - Trays
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