參數(shù)資料
型號(hào)： M58MR064D120ZC6T
廠商： 意法半導(dǎo)體
英文描述： 64 Mbit 4Mb x16, Mux I/O, Dual Bank, Burst 1.8V Supply Flash Memory
中文描述： 64兆位4Mb的x16插槽，復(fù)用的I / O，雙行，突發(fā)1.8V電源快閃記憶體
文件頁(yè)數(shù)： 3/52頁(yè)
文件大?。?/td> 399K
代理商： M58MR064D120ZC6T
11/52
M58MR064C, M58MR064D
Table 10. Commands
Hex Code
Command
00h
Invalid Reset
01h
Protect Confirm
03h
Write Read Configuration Register
Confirm
10h
Alternative Program Set-up
20h
Block Erase Set-up
2Fh
Lock Confirm
30h
Double Word Program Set-up
40h
Program Set-up
50h
Clear Status Register
55h
Tetra Word Program Set-up
60h
Protect Set-up and Write Read
Configuration Register
70h
Read Status Register
80h
Bank Erase Set-up
90h
Read Electronic Signature
98h
CFI Query
B0h
Program/Erase Suspend
C0h
Protection Program and Lock Protection
Program
D0h
Program/Erase Resume, Erase Confirm
or Unprotect Confirm
FFh
Read Array
INSTRUCTIONS AND COMMANDS
Eighteen instructions are available (see Tables 10
and 11) to perform Read Memory Array, Read Sta-
tus Register, Read Electronic Signature, CFI Que-
ry, Block Erase, Bank Erase, Program, Tetra Word
Program, Double Word Program, Clear Status
Register,
Program/Erase
Suspend,
Program/
Erase Resume, Block Protect, Block Unprotect,
Block Lock, Protection Register Program, Read
Configuration Register and Lock Protection Pro-
gram.
Status Register output may be read at any time,
during programming or erase, to monitor the
progress of the operation.
An internal Command Interface (C.I.) decodes the
instructions while an internal Program/Erase Con-
troller (P/E.C.) handles all timing and verifies the
correct execution of the Program and Erase in-
structions. P/E.C. provides a Status Register
whose bits indicate operation and exit status of the
internal algorithms. The Command Interface is re-
set to Read Array when power is first applied,
when exiting from Reset or whenever VDD is lower
than VLKO. Command sequence must be followed
exactly. Any invalid combination of commands will
reset the device to Read Array.
Read (RD)
The Read instruction consists of one write cycle
(refer to Device Operations section) and places
the addressed bank in Read Array mode. When a
device reset occurs, the memory is in Read Array
as default. A read array command will be ignored
while a bank is programming or erasing. However
in the other bank a read array command will be ac-
cepted.
Read Status Register (RSR)
A bank's Status Register indicates when a pro-
gram or erase operation is complete and the suc-
cess or failure of operation itself. Issue a Read
Status Register Instruction (70h) to read the Sta-
tus Register content of the addressed bank. The
status of the other bank is not affected by the com-
mand. The Read Status Register instruction may
be issued at any time, also when a Program/Erase
operation is ongoing. The following Read opera-
tions output the content of the Status Register of
the addressed bank. The Status Register is
latched on the falling edge of E or G signals, and
canbereaduntil E or G returns to VIH. Either E or
G must be toggled to update the latched data.
Read Electronic Signature (RSIG)
The Read Electronic Signature instruction con-
sists of one write cycle (refer to Device Operations
section) giving the command 90h to an address
within the bank A. A subsequent read in the ad-
dress of bank A will output the Manufacturer Code,
theDeviceCode, theprotectionStatus of Blocks
of bank A, the Die Revision Code, the Protection
Register, or the Read Configuration Register (see
Table 9).
If the first write cycle of Read Electronic Signature
instruction is issued to an address within the bank
B, a subsequent read in an address of bank B will
output the protection Status of Blocks of bank B.
The status of the other bank is not affected by the
command (see Table 8).
See Tables 5, 6, 7 and 8 for the valid address. The
Electronic Signature can be read from the memory
allowing programming equipment or applications
to automatically match their interface to the char-
acteristics of M58MR064C and M58MR064D.
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