參數(shù)資料
型號: M37902FGCGP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機
文件頁數(shù): 96/143頁
文件大?。?/td> 1463K
代理商: M37902FGCGP
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
96
Fig. 101 Bit configuration of particular function select register 1
Fig. 102 Bit configuration of watchdog timer frequency select register
7
6
5
4
3
2
1
0
Particular function select register 1
STP-instruction-execution status bit
(Note 1)
0: Normal operation.
1: STP instruction has been executed.
WIT-instruction-execution status bit
(Note 1)
0: Normal operation.
1: WIT instruction has been executed.
Standby state select bit
0: External bus
1: Programmable I/O port
System clock stop select bit at WIT
(Note 2)
0: In wait mode, system clock f
sys
is active.
1: In wait mode, system clock f
sys
is stopped.
Address output select bit
0: Address changes depending on bus access.
1: Address changes only at access to external address.
Timer B2 clock source select bit
In event counter mode:
0: Clock input from pin TB2
IN
is counted.
1: fX
32
(f(X
IN
)/32) is counted.
Address
63
16
Notes 1:
At power-on reset, this bit becomes
0
. At hardware reset or software reset, this bit
retains the value just before reset. Even when
1
is written, the bit status will not change.
2:
Setting this bit to
1
must be performed just before execution of the WIT instruction.
Also, after the wait state is terminated, this bit must be cleared to
0
immediately.
7
6
5
4
3
2
1
0
Watchdog timer frequency select register
Watchdog timer frequency select bit
0 : Select Wf
512
1 : Select Wf
32
Watchdog timer clock source select bits at STP termination
0 0 : fX
32
0 1 : fX
16
1 0 : fX
128
1 1 : fX
64
Address
61
16
down with one of the above divide clocks, fX
16
to fX
128
, after the os-
cillation circuit and PLL circuit have been restarted their operations
owing to an interrupt. The most significant bit of the watchdog timer
reaching
0
, supply of
φ
BIU
and
φ
CPU
restarts.
On the other hand, when the external clock input select bit =
1
and
the system clock select bit =
0
, supply of
φ
BIU
and
φ
CPU
will restart
immediately after the oscillation circuit has been restarted their op-
erations owing to an interrupt. (In actual fact, after the selected one
of the above divide clocks, fX
16
to fX
128
, has been changed from
H
to
L
, this supply will restart.)
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