![](http://datasheet.mmic.net.cn/280000/M37902F8CHP_datasheet_16084061/M37902F8CHP_48.png)
M37902FCCHP, M37902FGCHP, M37902FJCHP
48
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Interrupts caused by the address matching detection and when di-
viding by zero are software interrupts and are not included in Figure
36.
Other interrupts previously mentioned are A-D converter, UART, etc.
interrupts. The priority of these interrupts can be changed by chang-
ing the priority level in the corresponding interrupt control register by
software.
Figure 37 shows a diagram of the interrupt priority detection circuit
When an interrupt is caused, each interrupt device compares its own
priority with the priority from above and if its own priority is higher,
then it sends the priority below and requests the interrupt. If the pri-
orities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is
“
0
”
. The request is not accepted if flag I is
“
1
”
. The reset, NMI,
and watchdog timer interrupts are not affected by the interrupt dis-
able flag I.
When an interrupt is accepted, the contents of the processor status
register (PS) is saved to the stack and the interrupt disable flag I is
set to
“
1
”
.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to
“
0
”
and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of the
accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting the
interrupt disable flag I to
“
0
”
and enable further interrupts.
For reset, watchdog timer, zero divide, NMI, and address match de-
tection interrupts, which do not have an interrupt control register, the
processor interrupt level (IPL) is set as shown in Table 10.
Table 9. Addresses of interrupt control registers
Interrupt control registers
INT
3
interrupt control register
INT
4
interrupt control register
A-D interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
0
interrupt control register
INT
1
interrupt control register
INT
2
interrupt control register
Addresses
00006E
16
00006F
16
000070
16
000071
16
000072
16
000073
16
000074
16
000075
16
000076
16
000077
16
000078
16
000079
16
00007A
16
00007B
16
00007C
16
00007D
16
00007E
16
00007F
16
The interrupt request bit and the interrupt priority level of each inter-
rupt source are sampled and latched at each operation code fetch
cycle while f
sys
is
“
H
”
. However, no sampling pulse is generated until
the cycles whose number is selected by software has passed, even
if the next operation code fetch cycle is generated. The detection of
an interrupt which has the highest priority is performed during that
time.
Fig. 36 Interrupt priority
Fig. 37 Interrupt priority detection
Watchdog
timer
NMI
Priority is determined by hardware
A-D converter, UART, etc. interrupts
Priority can be changed by software inside
.
Reset
Reset
A-D
UART1 transmit
UART1 receive
UART0 transmit
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
INT
2
NMI
Watchdog timer
IPL
Interrupt request
Level 0
Interrupt disable flag I
INT
3
INT
1
INT
0
INT
4