參數(shù)資料
型號(hào): M37902FGCGP
廠商: Mitsubishi Electric Corporation
英文描述: SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述: 單片16位CMOS微機(jī)
文件頁(yè)數(shù): 57/143頁(yè)
文件大?。?/td> 1463K
代理商: M37902FGCGP
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57
M37902FCCHP, M37902FGCHP, M37902FJCHP
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
(3) One-shot pulse mode [10]
Figure 51 shows the bit configuration of the timer Ai mode register
during one-shot pulse mode. In one-shot pulse mode, bit 0 and bit 5
must be
0
and bit 1 and bit 2 must be
1
.
The trigger is enabled when the count start bit is
1
. The trigger can
be generated by software or it can be input from the TAi
IN
pin. Soft-
ware trigger is selected when bit 4 is
0
and the input signal from the
TAi
IN
pin is used as the trigger when it is
1
.
Bit 3 is used to determine whether to trigger at the fall of the trigger
signal or at the rise. The trigger is at the fall of the trigger signal when
bit 3 is
0
and at the rise of the trigger signal when it is
1
.
Software trigger is generated by setting
1
to a bit in the one-shot
start register. Each bit corresponds to each timer.
Figure 52 shows the bit configuration of the one-shot start register.
As shown in Figure 53, when a trigger signal is received, the counter
counts the clock selected by bits 6 and 7 and the contents of the
timer A clock division select register. (Set Table 12.)
If the contents of the counter is not 0000
16
, the TAi
OUT
pin goes
H
when a trigger signal is received. The count direction is decrement.
When the counter reaches 0001
16
, the TAi
OUT
pin goes
L
and
count is stopped. The contents of the reload register is transferred to
the counter. At the same time, an interrupt request signal is gener-
ated and the interrupt request bit in the timer Ai interrupt control reg-
ister is set. This is repeated each time a trigger signal is received.
The output pulse width is
If the count start flag is
0
, TAi
OUT
goes
L
. Therefore, the value cor-
responding to the desired pulse width must be written to timer Ai be-
fore setting the timer Ai count start bit.
As shown in Figure 54, a trigger signal can be received before the
operation for the previous trigger signal is completed. In this case,
the contents of the reload register is transferred to the counter by the
trigger and then that value is decremented.
Except when retriggering while operating, the contents of the reload
register are not transferred to the counter by triggering.
When retriggering, there must be at least one timer count source
cycle before a new trigger can be issued.
Data write is performed in the same way as for timer mode.
When data is written in timer Ai halted, it is also written to the reload
register and the counter.
When data is written to timer Ai which is busy, the data is written to
the reload register, but not to the counter. The counter is reloaded
with new data from the reload register at the next reload time.
Undefined data is read when timer Ai is read.
1
pulse frequency of the selected clock
×
(counter
s value at the time of trigger).
Fig. 51 Bit configuration of timer Ai mode register during one-shot
pulse mode
Fig. 52 Bit configuration of one-shot start register
7 6 5 4 3 2 1 0
0
0
1
1
1 0 : Always
10
in one-shot pulse mode
1 : Always
1
in one-shot pulse mode
0
×
: Software trigger
1 0 : Trigger at the falling edge of TAi
IN
input
1 1 : Trigger at the rising edge of TAi
IN
input
0 : Always
0
in one-shot pulse mode
Clock source select bits
(See Table 12.)
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer A3 mode register
Timer A4 mode register
Addresses
56
16
57
16
58
16
59
16
5A
16
7 6 5 4 3 2 1 0
0
Timer A0 one-shot start bit
Timer A1 one-shot start bit
Timer A2 one-shot start bit
Timer A3 one-shot start bit
Timer A4 one-shot start bit
Must be fixed to
0
.
One-shot start register
Address
42
16
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