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參數(shù)資料
| 型號： | M37902FGCGP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單片16位CMOS微機 |
| 文件頁數(shù)： | 95/143頁 |
| 文件大?。?/td> | 1463K |
| 代理商： | M37902FGCGP |
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95
M37902FCCHP, M37902FGCHP, M37902FJCHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
STANDBY FUNCTION
The standby function provides the stop (hereafter called STP) and
the wait (hereafter called WIT) mode. These modes are used to save
the power dissipation of the system, by stopping oscillation or sys-
tem clock in the case that the CPU needs not be operating.
The microcomputer enters the STP or WIT mode by executing the
STP or WIT instruction, and either mode is terminated by acceptance
of an interrupt request or reset.
To terminate the STP or WIT mode by an interrupt request, the inter-
rupt to be used for termination of the STP or WIT mode must be en-
abled in advance to execution of the STP or WIT instruction. The
interrupt priority level of this interrupt is required to be higher than the
processor interrupt priority level (IPL) of the routine where the STP
or WIT instruction will be executed.
Figures 100 to 102 show the bit configurations of the particular func-
tion select registers 0, 1, and watchdog timer frequency select regis-
ter respectively. Setting the STP instruction invalidity select bit (bit 0
of the particular function select register 0) to
“
1
”
invalidates the STP
instruction, and the STP instruction will be ignored. Since the above
bit is cleared to
“
0
”
after reset is removed, however, the STP instruc-
tion is valid.
The STP- or the WIT-instruction-execution status bit (bit 0 or 1 of the
particular function select register 1) is set to
“
1
”
by the execution of
the STP or the WIT instruction, and so, after the STP or WIT mode
has been terminated, each bit will indicate that the STP or WIT in-
struction has been executed. Accordingly, each of these bits must be
cleared to
“
0
”
by software at termination of the STP or the WIT mode.
Table 17 explains the microcomputer
’
s operation in the STP and WIT
modes.
The external bus fixation function can also be provided. This function
enables the user to specify the states of the external bus and the bus
control signals in the memory expansion and the microprocessor
mode in the STP or WIT mode. For more information, refer to the
section on the power saving function.
STP mode
The execution of the STP instruction stops the oscillation circuit and
PLL circuit. It also stops input clock fX
IN
, system clock f
sys
,
φ
BIU
,
φ
CPU
, and peripheral devices
’
clocks f
1
to f
4096
, Wf
32
and Wf
512
in
the
“
L
”
state, and divide clocks fX
16
to fX
128
in the
“
H
”
state. In the
watchdog timer,
“
FFF
16
”
is automatically set. As shown in Figure 98,
any one of divide clocks fX
16
to fX
128
, which is selected by the
watchdog timer clock source select bits at STP termination (bits 6
and 7 of the watchdog timer frequency select register), becomes the
watchdog timer
’
s clock source.
In the STP mode, the A-D converter and watchdog timer, which uses
peripheral devices
’
clocks f
1
to f
4096
, Wf
32
and Wf
512
, are stopped.
At this time, timers A and B operate only in the event counter mode,
and serial I/O communication is active while an external clock is se-
lected.
The STP mode is terminated by acceptance of an interrupt request
or reset, and the oscillation circuit and PLL circuit restart their opera-
tions. Input clock fX
IN
, system clock f
sys
, and peripheral devices
’
clocks f
1
to f
4096
, Wf
32
and Wf
512
are also supplied.
When the STP mode is terminated by reset, supply of
φ
BIU
and
φ
CPU
starts immediately after the oscillation circuit and PLL circuit restart
their operations. Therefore, the reset input must be raised
“
H
”
after
the operation-stabilizing time for these circuits has passed.
The following two modes are available in order to terminate the STP
mode by an interrupt:
(1) The watchdog timer is used in order to measure the period from
the operation restart of the oscillation circuit and PLL circuit until
the supply start of
φ
BIU
and
φ
CPU.
(2) The supply of
φ
BIU
and
φ
CPU
is started immediately after the op-
eration restart of the oscillation circuit and PLL circuit.
When the external clock input select bit (bit 1 of the particular func-
tion select register 0) =
“
0
”
or the system clock select bit (bit 5 of the
clock control register) =
“
1
”
, the watchdog timer will start counting
Mode
WIT
System clock
stop select bit
at WIT
Active
(Note 1)
Oscillation
circuit
Operations of function while WIT, STP modes
f
sys
,
φ
1
,
f
1
to f
4096
“
0
”
Active
STP
Wf
32
, Wf
512
φ
BIU
,
φ
CPU
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Peripheral devices using f
1
to f
4096
, Wf
32
, Wf
512
Timers A, B, Serial I/O, A-D converter: Operation is enabled.
(Watchdog timer: Stopped.)
Timers A, B: Operation is enabled only in the event
counter mode.
Serial I/O: Operation is enabled only while an external
clock is selected.
A-D converter: Stopped.
(Watchdog timer: Stopped.)
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Active
(Note 1)
“
1
”
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Stopped
(
“
L
”
)
Stopped
Timers A, B: Operation is enabled only in the event
counter mode.
Serial I/O: Operation is enabled only while an external
clock is selected.
A-D converter: Stopped.
(Watchdog timer: Stopped.)
PLL circuit
Active
(Note 2)
Active
(Note 2)
Stopped
Notes 1:
When the external clock input select bit =
“
1
”
, the oscillation circuit stops. Also, clock input from pin X
IN
is available.
2:
When the PLL operation enable bit =
“
0
”
, the PLL circuit stops.
—
Table 17. Microcomputer
’
s operation in STP and WIT modes
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|---|---|
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