參數(shù)資料
型號(hào)： M37902FGCGP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
中文描述： 單片16位CMOS微機(jī)
文件頁(yè)數(shù)： 136/143頁(yè)
文件大?。?/td> 1463K
代理商： M37902FGCGP
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Corrections and
Page
Page 18,
Table 1
nstruction
queue buff
Supplement
ar
Erro
y
Explanation
r
for M37902FxC Dat
asheet (REV.
Correction
B) NO.4
(4/11)
b31
b0
DB
Data buff
er
b31
b0
DQ
Data buff
er
Page 18,
Fig. 11
#
Page 26,
Fig. 18,
Notes 1
N
ction as I/O
o
t
e
s
1
:
The number of bus cycles is determi-
ned by the follow
ing bits:
Notes 1:
The bus cycle type is determined by the
following bits:
Page 31,
ight column
Line 5
R
. Therefore, ports P0 or P
pin
s
for the address bus,
4
,
P10, P11 fun-
. Therefore, ports P0 to P4, P10, P11 fun-
ction as I/O pins for the address bus,
Mode
(Note 1)
Pin MD0
Processor mode
(Note 2)
Page 33,
Table 5
Mode
(Note 1)
Pin MD0
(Note 2)
Processor
mode bi
t
s
Page 35,
Fig. 24,
Note
N
o
t
e
s
1
:
W
While V
C
(Fixed to “1”.)
h
i
l
e
V
S
S
C
, bit 1 is cleared to “0”.
, bit 1
i
s
se
t
to “1” at reset.
Notes 1:
While V
SS
, this bit’s state is cleared
to “0” at reset. While V
CC
, this bit’s
state is set to “1” at reset. (Fixed to “1”.)
3:
While V
SS
, bit 7 is cleared to “0”.
While V
CC
, bit 7 is set to “1” at reset.
3:
While V
SS
, this bit’s state is cleared
to “0” at reset. While V
CC
, this bit’s
state is set to “1” at reset.
#
4
:
W
V
C
h
i
l
e
V
S
S
,
on the ot
these bits ar
h
er
hand, t
e cleared to
h
ese
“0”.
are set
Whil
to “
e
1
C
,
b
its
”
.
4:
While V
SS
, each of these bits is “0” at reset. While
V
CC
, on the other hand, each of these bits is “1”
at reset.
Data buff
er
Temporari
and external are
writeen to internal
t
y stores data which has bee
as
b
y
the BIU or which is to be
me
mory,
n
,
.
Temporarily stores data which has been ,
and external areas by the BIU; or temporarily
stores data which is to be written to internal
memory, .
#
I
er
Temporarity stores an instruction which .
Temporarily stores an instruction which .
Processor mode regi
st
er 1
1
0
2
4
3
5
6
7
Recove
er
bit
(Note 6)
ry-cycle-i
nsert
sel
ect
bi
t
Int
nal ROM
b
us
cycl
e
sel
ect
Page 36,
Fig. 25
#
Processor mode regi
st
er 1
1
0
2
4
3
5
6
7
Recove
(N
o
te
er
bit
(Note 7)
ry-cycle-i
6)
nsert
sel
ect
bi
t
Int
nal ROM
b
us
cycl
e
sel
ect
2:
A
once. During the
swi
t
ch this bit’s contents.
ft
er r
eset, t
hi
s
b
it’s cont
software execution, be
en
t
s can be switched only
su
r
e not t
o
2:
A
softwar
ft
er r
eset, t
e
hi
s
b
t
i
it
on,
can be set only once.
be sure not
D
ur
i
ng t
he
execu
to change this bit.
5:
In the memory expansion or microprocessor mode, if
this bit’s contents is switched from “1” to “0”, this bit
will be cleared to “0”. After this clearance, this bit
cannot return to “1”. If it is necessary to set this bit to
“1”, be sure to reset the microcomputer.
5:
A
Once t
they cannot
ft
er r
eset, t
he
he
bi
be
se
s have been clea
set to
“1”
bi
t
s can be set
to “1”
ed to “
(Fi
xed t
only once.
0” f
rom
o “0”
.)
se
t
r
“1”,
ag
ain.
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