![](http://datasheet.mmic.net.cn/280000/M37754M8C-XXXGP_datasheet_16084055/M37754M8C-XXXGP_75.png)
75
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37754M8C-XXXGP, M37754M8C-XXXHP
M37754S4CGP, M37754S4CHP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
OUTPUT FUNCTION OF CHIP SELECT SIGNAL
Ports P9
0
to P9
4
can output the chip select signals CS
0
to CS
4
ac-
cording to the contents of chip select control register and chip select
area register. Bits 0 to 3 of chip select control register select either
chip select output (or addresses A
20
to A
22
output) or port function.
Additionally, bits 0 to 2 of chip select area register select the area in-
tended for each chip select signal.
Figure 87 shows the bit configuration of chip select control register
and Figure 88 shows that of chip select area register. Figure 89
shows the chip select areas.
The bus cycle of CS
3
and CS
4
can be selected with bits 4 to 7 of chip
select control register. That selection is valid regardless of the bus
cycle select bits of processor mode register 1. Additionally, that bus
cycle selection of CS
3
and CS
4
is valid when selecting port function
with the CS
3
and CS
4
function select bits.
When accessing addresses in which the chip select area specified
by bits 0 to 2 of chip select area register and the internal memory
area overlap one another, chip select signals are not output. In this
case, its bus cycle is the cycle of internal memory area access.
It is possible to make the chip select output floating during Hold
state. That is realized by clearing the corresponding bit of port P9
direction register (address 15
16
) to “0” and bits 0 to 2 of waveform
output mode register (address 1A
16
) to “000”. The timing of Hold
start and termination is the same as that of addresses A
0
to A
19
. (Re-
fer to section on processor mode.)
ADDRESS OUTPUT FUNCTION
Port P9
1
to P9
3
can output the high-order addresses (A
20
to A
22
) ac-
cording to bits 1 and 2 of chip select control register, and bits 6 and 7
of chip select area register.
About signal pairs of A
20
and CS
1
, A
21
and CS
2
, and A
22
and CS
3
,
only one signal can be output. It is because chip select signals CS
1
to CS
3
output are common to ports P9
1
to P9
3
and addresses A
20
to
A
22
output.
It is possible to make the address output floating during Hold state.
That is realized by clearing the corresponding bit of port P9 direction
register (address 15
16
) to “0” and bits 0 to 2 of waveform output
mode register (address 1A
16
) to “000”. The timing of Hold start and
termination is the same as that of addresses A
0
to A
19
. (Refer to sec-
tion on processor mode.)
Fig. 87 Chip select control register bit configuration
Address
62
16
CS
0
function select bit
(Note 1)
0 : Port P9
0
function
1 : CS
0
output
CS
4
function select bit
0 : Port P9
4
function
1 : CS
4
output
CS
1
, CS
2
function select bit
(Note 2)
0 : Port P9
1
, P9
2
function
1 : CS
1,
CS
2
output or A
20
, A
21
output
CS
3
function select bit
(Note 2)
0 : Port P9
3
function
1 : CS
3
output or A
22
output
7
6
5
4
3
2
1
0
CS
3
bus cycle select bits
b5 b4 In high-speed In low-speed
0 0 : 5-
φ
access Do not select.
0 1 : 4-
φ
access 4-
φ
access
1 0 : 3-
φ
access 3-
φ
access
1 1 : Do not select. 2-
φ
access
CS
4
bus cycle select bits
b7 b6 In high-speed In low-speed
0 0 : 5-
φ
access Do not select.
0 1 : 4-
φ
access 4-
φ
access
1 0 : 3-
φ
access 3-
φ
access
1 1 : Do not select. 2-
φ
access
Notes 1 :
At reset, bit 0 becomes “0” when the CNVss pin’s level is “L”;
bit 0 becomes “1” when the CNVss pin’s level is “H”.
2 :
Bits 6 and 7 of chip select area register (address 63
16
) specify
whether the chip select signal or address is output.
Chip select control register