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參數(shù)資料
| 型號(hào)： | L80225 |
| 英文描述： | L80225 10/100 MbpsTX/10BT Ethernet Physical Layer Device (PHY) technical manual 4/02 |
| 中文描述： | L80225 10/100 MbpsTX/10BT以太網(wǎng)物理層器件（PHY）技術(shù)手冊(cè)4月2日 |
| 文件頁(yè)數(shù)： | 55/192頁(yè) |
| 文件大?。?/td> | 1306K |
| 代理商： | L80225 |
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Draft 6/5/00
Block Diagram Description
2-35
Copyright 2000 by LSI Logic Corporation. All rights reserved.
2.2.11.7 AutoNegotiation Reset
Appropriately setting the AutoNegotiation Reset (ANEG_RST) bit in the
MI serial port Control register can initiate or reset the AutoNegotiation
algorithm at any time.
2.2.12 Link Indication
Receive link detect activity can be monitored through the Link Detect bit
(LINK) in the MI serial port Status register and the Link Fail Detect bit
(LNK_FAIL) in the Status Output register. Link detect activity can also be
programmed to appear on the PLED3n or PLED0n pins. To do this,
appropriately set the Programmable LED Output Select bits in the MI
serial port Configuration 2 register as shown in
Table 2.9
. When either
the PLED3n or PLED0n pins are programmed to be a link detect output,
they are asserted LOW whenever the device is in the Link Pass State.
The PLED3 output is an open-drain pin with pullup resistor and can drive
an LED from V
DD
. The PLED0 output has both pullup and pulldown
driver transistors in addition to a weak pullup resistor, so it can drive an
LED from either V
DD
or GND. Both the PLED3n and PLED0n outputs can
also drive another digital input. Refer to
Section 2.2.14, “LED Drivers,”
page 2-37
for a description on how to program the PLED[3:0]n pins and
their default values.
2.2.13 Collision
Collisions occur whenever transmit and receive operations occur
simultaneously while the device is in Half-Duplex mode.
2.2.13.1 100 Mbits/s
In 100 Mbits/s operation, a collision occurs and is sensed whenever there
is simultaneous transmission (packet transmission on TPO+/-) and
reception (non-idle symbols detected at the TPI+/- input). When a
collision is detected, the COL output is asserted, TP data continues to
be transmitted on the twisted-pair outputs, TP data continues to be
received on the twisted-pair inputs, and internal CRS loopback is
disabled. After a collision is in process, CRS is asserted and stays
asserted until the receive and transmit packets that caused the collision
are terminated.
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| L80223 | 10BASE-T/100BASE-TX/FX Ethernet Physical Layer Device (PHY)(10BASE-T/100BASE-TX/FX 以太網(wǎng)物理層處理器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| L80225/B | 制造商:LSI Corporation 功能描述:TRANSITION TO P/N 68080A1 - Bulk |
| L80225/C | 制造商:LSI Corporation 功能描述:PN may be NE SA DW 制造商:LSI Corporation 功能描述:L80225/C |
| L80225FR | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, two |
| L80225VF2 | 制造商:LAUREL ELECTRONICS 功能描述:Laureate 1/8 DIN multi-function counter / timer, universal 85-264 Vac power, two |
| L80227 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:10BASE-T/ 100BASE-TX Ethernet PHY |
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