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L29S800F
PRELIMINARY
A
8MEGABIT (1M×8 /512K×16)
3 VOLT CMOS FLASH MEMERY
LinkSmart
■
GENERAL DESCRIPTION
The L29S800F/-B are a 8M-bit, 3.0 V-only Flash memory organized as 1M bytes of 8 bits each or 512K
words of 16 bits each. The L29S800F/-B are offered in a 48-pin TSOP(I) package, These devices are
designed to be programmed in-system with the standard system 3.0 V V
CC
supply. 12.0 V V
PP
and 5.0
V V
CC
are not required for write or erase operations. The devices can also be reprogrammed in standard
EPROM programmers.
The standard L29S800F/-B offer access times 70 ns and 120 ns, allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the devices have separate chip
enable (
CE
), write enable (
WE
), and output enable (
OE
) controls.
The L29S800F/-B are pin and command set compatible with JEDEC standard E
2
PROMs. Commands
are written to the command register using standard microprocessor write timings. Register contents
serve as input to an internal state-machine which controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed for the programming and erase operations.
Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices.
The L29S800F/-B are programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse
widths and verifies proper cell margin. Typically, each sector can be programmed and verified in about
0.5 seconds. Erase is accomplished by executing the erase command sequence. This will invoke the
Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array if it
is not already programmed before executing the erase operation. During erase, the devices
automatically time the erase pulse widths and verify proper cell margin.
A sector is typically erased and verified in 1.0 second. (If already completely preprogrammed.)
The devices also feature a sector erase architecture. The sector mode allows each sector to be erased
and reprogrammed without affecting other sectors. The L29S800F/-B are erased when shipped from
the factory.
The devices feature single 3.0 V power supply operation for both read and write functions. Internally
generated and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically inhibits write operations on the loss of power. The end of program or erase is
detected by
Data
Polling of DQ
7
, by the Toggle Bit feature on DQ
6
, or the RY/
BY
output pin. Once the
end of a program or erase cycle has been completed, the devices internally reset to the read mode.
LST’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest
levels of quality, reliability, and cost effectiveness. The L29S800F/-B memories electrically erase the
entire chip or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words
are programmed one byte/word at a time using the EPROM programming mechanism of hot electron
injection.
3
071802