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參數(shù)資料
| 型號： | L29S800F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8MEGABIT (1M】8 /512K】16) 3 VOLT CMOS FLASH MEMERY |
| 中文描述： | 8MEGABIT（100萬】8 / 16】為512k）3伏的CMOS閃存MEMERY |
| 文件頁數(shù)： | 24/54頁 |
| 文件大?。?/td> | 797K |
| 代理商： | L29S800F |
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L29S800F
PRELIMINARY
A
8MEGABIT (1M×8 /512K×16)
3 VOLT CMOS FLASH MEMERY
LinkSmart
24
071802
Mode
DQ
7
DQ
6
DQ
2
Program
7
DQ
Toggle
1
Erase
0
Toggle
Toggle
Erase-Suspend Read
(Erase-Suspended Sector)
(Note 1)
1
1
Toggle
Erase-Suspend Program
7
DQ
Toggle (Note 1)
1 (Note 2)
Notes:
1. Performing successive read operations from any address will cause DQ
6
to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate
logic “1” at the DQ
2
bit. However, successive reads from the erase-suspended sector will cause DQ
2
to toggle.
RY/
BY
Ready/Busy
The L29S800F/-B provide a RY/
BY
open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the devices are
busy with either a program or erase operation. If the output is high, the devices are ready to accept any
read/write or erase operation. When the RY/
BY
pin is low, the devices will not accept any additional
program or erase commands. If the L29S800F/-B are placed in an Erase Suspend mode, the RY/
BY
output
will be high.
During programming, the RY/
BY
pin is driven low after the rising edge of the fourth
WE
pulse. During an
erase operation, the RY/
BY
pin is driven low after the rising edge of the sixth
WE
pulse. The RY/
BY
pin
will indicate a busy condition during the
RESET
pulse. Refer to Figure 11 and 12 for a detailed timing
diagram. The RY/
BY
pin is pulled high in standby mode.
Since this is an open-drain output, RY/
BY
pins can be tied together in parallel with a pull-up resistor to
V
CC
.
Byte/Word Configuration
The
BYTE
pin selects the byte (8-bit) mode or word (16-bit) mode for the L29S800F/-B devices. When this
pin is driven high, the devices operate in the word (16-bit) mode. The data is read and programmed at DQ
0
to DQ
15
. When this pin is driven low, the devices operate in byte (8-bit) mode. Under this mode, the
DQ
15
/A
-1
pin becomes the lowest address bit and DQ
8
to DQ
14
bits are tri-stated. However, the command
bus cycle is always an 8-bit operation and hence commands are written at DQ
0
to DQ
7
and the DQ
8
to DQ
15
bits are ignored. Refer to Figures 13, 14 and 15 for the timing diagram.
Data Protection
The L29S800F/-B are designed to offer protection against accidental erasure or programming caused by
spurious system level signals that may exist during power transitions. During power up the devices
automatically reset the internal state machine in the Read mode. Also, with its control register architecture,
alteration of the memory contents only occurs after successful completion of specific multi-bus cycle
command sequences.
The devices also incorporate several features to prevent inadvertent write cycles resulting form V
CC
power-up and power-down transitions or system noise.
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