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L29S800F
PRELIMINARY
A
8MEGABIT (1M×8 /512K×16)
3 VOLT CMOS FLASH MEMERY
LinkSmart
16
071802
Table 8 L29S800F/-B Extended Command Definitions
First Bus
Write Cycle
Write
Cycles
Req’d
Second Bus
Write Cycle
Third Bus
Write Cycle
Fifth Bus
Write Cycle
Command
Sequence
Bus
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Word
555H
2AAH
555H
Set to
Fast Mode
Byte
3
AAAH
AAH
555H
55H
AAAH
20H
—
—
Word
XXXH
Fast
Program
*1
Byte
2
XXXH
A0H
PA
PD
—
—
—
—
Word
XXXH
XXXH
Reset from
Fast Mode
*1
Byte
2
XXXH
90H
XXXH
F0H*
3
—
—
—
—
Word
Extended
Sector
Protect
*2
Byte
4
XXXH
60H
SPA
60H
SPA
40H
SPA
SD
SPA : Sector address to be protected. Set sector address (SA) and (A
6
, A
1
, A
0
) = (0, 1, 0).
SD : Sector protection verify data. Output 01H at protected sector addresses and output 00H at
unprotected sector addresses.
*1:This command is valid while Fast Mode.
*2:This command is valid while
RESET
=V
ID
.
*3:This data "00H" is also acceptable.
Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the devices to the read mode. Table 7 defines the valid register command sequences. Note that the
Erase Suspend (B0H) and Erase Resume (30H) commands are valid only while the Sector Erase
operation is in progress. Moreover both Read/Reset commands are functionally equivalent, resetting
the device to the read mode. Please note that commands are always written at DQ
0
to DQ
7
and DQ
8
to DQ
15
bits are ignored.
Read/Reset Command
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
5
= 1) to read/reset mode, the
read/reset operation is initiated by writing the Read/Reset command sequence into the command
register. Microprocessor read cycles retrieve array data from the memory. The devices remain
enabled for reads until the command register contents are altered.
The devices will automatically power-up in the read/reset state. In this case, a command sequence is
not required to read data. Standard microprocessor read cycles will retrieve array data. This default
value ensures that no spurious alteration of the memory content occurs during the power transition.
Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.