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參數(shù)資料
| 型號： | L29S800F |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 8MEGABIT (1M】8 /512K】16) 3 VOLT CMOS FLASH MEMERY |
| 中文描述： | 8MEGABIT（100萬】8 / 16】為512k）3伏的CMOS閃存MEMERY |
| 文件頁數(shù)： | 25/54頁 |
| 文件大小： | 797K |
| 代理商： | L29S800F |
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L29S800F
PRELIMINARY
A
8MEGABIT (1M×8 /512K×16)
3 VOLT CMOS FLASH MEMERY
LinkSmart
Low V
CC
Write Inhibit
25
071802
To avoid initiation of a write cycle during V
CC
power-up and power-down, a write cycle is locked out for V
CC
less than 2.3 V (typically 2.4 V). If V
CC
< V
LKO
, the command register is disabled and all internal
program/erase circuits are disabled. Under this condition the device will reset to the read mode. Subsequent
writes will be ignored until the V
CC
level is greater than V
LKO
. It is the users responsibility to ensure that the
control pins are logically correct to prevent unintentional writes when V
CC
is above 2.3 V.
If Embedded Erase Algorithm is interrupted, there is possibility that the erasing sector(s) cannot be used.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on
OE
,
CE
, or
WE
will not initiate a write cycle.
Logical Inhibit
Writing is inhibited by holding any one of
OE
= V
IL
,
CE
= V
IH
, or
WE
= V
IH
. To initiate a write cycle
CE
and
WE
must be a logical zero while
OE
is a logical one.
Power-Up Write Inhibit
Power-up of the devices with
WE
=
CE
= V
IL
and
OE
= V
IH
will not accept commands on the rising
edge of
WE
. The internal state machine is automatically reset to the read mode on power-up.
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