參數(shù)資料
型號(hào)： KSZ8862-16MQL-FX
廠商： Micrel Inc
文件頁數(shù)： 85/125頁
文件大?。?/td> 0K
描述： IC SWITCH ETH 2P 16BIT 128PQFP
標(biāo)準(zhǔn)包裝： 66
系列： KSZ8862
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
配用： 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱： 576-3271
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
62
M9999-040407-3.0
Bank 16 Receive Control Register (0x04): RXCR
This register holds control information programmed by the CPU to control the receive function.
Bit
Default Value
R/W
Description
15-11
-
RO
Reserved
10
0x0
RW
RXFCE Receive Flow Control Enable
When this bit is set, the KSZ8862M will acknowledge a PAUSE frame from the receive
interface; i.e., the outgoing packets are pending in the transmit buffer until the PAUSE
frame control timer expires. When this bit is cleared, flow control is not enabled.
9
0x0
RW
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received into the RX queue. When
reset, all CRC error frames are discarded.
8
-
RO
Reserved
7
0x0
RW
RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast frames.
6
0x0
RW
RXME Receive Multicast Enable
When this bit is set, the RX module receives all the multicast frames (including broadcast
frames).
5
0x0
RW
RXUE Receive Unicast
When this bit is set, the RX module receives unicast frames that match the 48-bit Station
MAC address of the module.
4
0x0
RW
RXRA Receive All
When this bit is set, the KSZ8862M receives all incoming frames, regardless of the frame’s
destination address.
3
0x0
RW
RXSCE Receive Strip CRC
When this bit is set, the KSZ8862M strips the CRC on the received frames. Once cleared,
the CRC is stored in memory following the packet.
2
0x0
RW
QMU Receive Multicast Hash-Table Enable
When this bit is set, this bit enables the RX function to receive multicast frames that pass
the CRC Hash filtering mechanism.
1
-
RO
Reserved
0
0x0
RW
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a running state. When reset, the
receive process is placed in the stopped state upon completing reception of the current
frame.
Bank 16 TXQ Memory Information Register (0x08): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
Bit
Default Value
R/W
Description
15-13
-
RO
Reserved
12-0
-
RO
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte. The TXQ memory is used
for both frame payload, control word. There is total 4096 bytes in TXQ.
Note: Software must be written to ensure that there is enough memory for the next transmit
frame including control information before transmit data is written to the TXQ.
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