參數(shù)資料
型號： KSZ8862-16MQL-FX
廠商： Micrel Inc
文件頁數(shù)： 71/125頁
文件大?。?/td> 0K
描述： IC SWITCH ETH 2P 16BIT 128PQFP
標準包裝： 66
系列： KSZ8862
控制器類型： 以太網(wǎng)開關(guān)控制器
接口： PCI
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應(yīng)商設(shè)備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
配用： 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱： 576-3271
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
5
M9999-040407-3.0
Aging...............................................................................................................................................................................29
Forwarding ......................................................................................................................................................................30
Switching Engine ............................................................................................................................................................32
MAC Operation ...............................................................................................................................................................32
Inter Packet Gap (IPG) ...................................................................................................................................................32
Back-Off Algorithm..........................................................................................................................................................32
Late Collision ..................................................................................................................................................................32
Legal Packet Size ...........................................................................................................................................................32
Flow Control....................................................................................................................................................................32
Half-Duplex Backpressure ..............................................................................................................................................32
Broadcast Storm Protection............................................................................................................................................33
Clock Generator..............................................................................................................................................................33
Bus Interface Unit (BIU)....................................................................................................................................................33
Asynchronous Interface ..................................................................................................................................................35
Synchronous Interface....................................................................................................................................................36
Summary.........................................................................................................................................................................36
BIU Implementation Principles........................................................................................................................................37
Queue Management Unit (QMU) ......................................................................................................................................38
Transmit Queue (TXQ) Frame Format ...........................................................................................................................38
Receive Queue (RXQ) Frame Format............................................................................................................................39
Advanced Switch Functions ............................................................................................................................................41
Spanning Tree Support...................................................................................................................................................41
IGMP Support .................................................................................................................................................................42
“IGMP” Snooping ........................................................................................................................................................42
“Multicast Address Insertion” in the Static MAC Table ...............................................................................................42
IPv6 MLD Snooping........................................................................................................................................................42
Port Mirroring Support ....................................................................................................................................................42
IEEE 802.1Q VLAN Support...........................................................................................................................................43
QoS Priority Support.......................................................................................................................................................43
Port-Based Priority..........................................................................................................................................................43
802.1p-Based Priority .....................................................................................................................................................43
DiffServ-Based Priority ...................................................................................................................................................44
Rate Limiting Support .....................................................................................................................................................44
MAC Filtering Function ...................................................................................................................................................45
Configuration Interface ...................................................................................................................................................45
EEPROM Interface .........................................................................................................................................................45
Loopback Support...........................................................................................................................................................46
Far-end Loopback ......................................................................................................................................................46
Near-end (Remote) Loopback ....................................................................................................................................46
CPU Interface I/O Registers .............................................................................................................................................48
I/O Registers ...................................................................................................................................................................48
Internal I/O Space Mapping ............................................................................................................................................49
Register Map: Switch and MAC/PHY...............................................................................................................................57
Bit Type Definition...........................................................................................................................................................57
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks) ..................................................................57
Bank 0 Base Address Register (0x00): BAR ..................................................................................................................57
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR..............................................57
Bank 0 Bus Error Status Register (0x06): BESR............................................................................................................58
Bank 0 Bus Burst Length Register (0x08): BBLR...........................................................................................................58
Bank 1 Reserved ............................................................................................................................................................58
Bank 2 Host MAC Address Register Low (0x00): MARL ...............................................................................................58
Bank 2 Host MAC Address Register Middle (0x02): MARM ..........................................................................................59
Bank 2 Host MAC Address Register High (0x04): MARH ..............................................................................................59
Bank 3 On-Chip Bus Control Register (0x00): OBCR ....................................................................................................59
Bank 3 EEPROM Control Register (0x02): EEPCR .......................................................................................................60
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