參數(shù)資料
型號： KSZ8862-16MQL-FX
廠商： Micrel Inc
文件頁數(shù)： 84/125頁
文件大?。?/td> 0K
描述： IC SWITCH ETH 2P 16BIT 128PQFP
標準包裝： 66
系列： KSZ8862
控制器類型： 以太網(wǎng)開關控制器
接口： PCI
安裝類型： 表面貼裝
封裝/外殼： 128-BFQFP
供應商設備封裝： 128-PQFP（14x20）
包裝： 托盤
產(chǎn)品目錄頁面： 1081 (CN2011-ZH PDF)
配用： 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱： 576-3271
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
61
M9999-040407-3.0
Bank 3 Bus Configuration Register (0x08): BCFG
This register is a read-only register. The bit 0 is automatically downloaded from bit 0 Configparm word of EEPROM, if pin
EEEN is high (enabled EEPROM)
Bit
Default Value
R/W
Description
15-1
0x0000
RO
Reserved
0
-
RO
Bus Configuration (only for KSZ8862-16 device)
1: bus width is 16 bits.
0: bus width is 8 bits.
(this bit is only avaiable when EEPROM is enabled)
Banks 4 – 15: Reserved
Except Bank Select Register (0xE).
Bank 16 Transmit Control Register (0x00): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
Bit
Default Value
R/W
Description
15
-
RO
Reserved
14
0x0
RW
Reserved
13
0x0
RW
Reserved
12-4
-
RO
Reserved
3
0x0
RW
TXFCE Transmit Flow Control Enable
When this bit is set, the QMU sends flow control pause frames from the host port if the RX
FIFO has reached its threshold.
Note: the SGCR3[5] in Bank 32 also needs to be enabled.
2
0x0
RW
TXPE Transmit Padding Enable
When this bit is set, the KSZ8862M automatically adds a padding field to a packet shorter
than 64 bytes.
Note: Setting this bit requires enabling the ADD CRC feature to avoid CRC errors for the
transmit packet.
1
0x0
RW
TXCE Transmit CRC Enable
When this bit is set, the KSZ8862M automatically adds a CRC checksum field to the end of
a transmit frame.
0
0x0
RW
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a running state. When
reset, the transmit process is placed in the stopped state after the transmission of the
current frame is completed.
Bank 16 Transmit Status Register (0x02): TXSR
This register keeps the status of the last transmitted frame.
Bit
Default Value
R/W
Description
15-6
0x000
RO
Reserved
5-0
-
RO
TXFID Transmit Frame ID
This field identifies the transmitted frame. All of the transmit status information in this
register belongs to the frame with this ID.
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