參數(shù)資料
型號: KSZ8862-16MQL-FX
廠商: Micrel Inc
文件頁數(shù): 69/125頁
文件大?。?/td> 0K
描述: IC SWITCH ETH 2P 16BIT 128PQFP
標(biāo)準(zhǔn)包裝: 66
系列: KSZ8862
控制器類型: 以太網(wǎng)開關(guān)控制器
接口: PCI
安裝類型: 表面貼裝
封裝/外殼: 128-BFQFP
供應(yīng)商設(shè)備封裝: 128-PQFP(14x20)
包裝: 托盤
產(chǎn)品目錄頁面: 1081 (CN2011-ZH PDF)
配用: 576-1638-ND - BOARD EVALUATION KSZ8862-10FL
576-1637-ND - BOARD EVALUATION KSZ8862-100FX
其它名稱: 576-3271
Micrel, Inc.
KSZ8862-16/32MQL
April 2007
48
M9999-040407-3.0
CPU Interface I/O Registers
The KSZ8862M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O
registers. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is
used for configuring operational settings, reading or writing control, status information, and transferring packets by reading
and writing through the packet data registers.
I/O Registers
Input/Output (I/O) registers are limited to 16 locations as required by most ISA bus-based systems; therefore, registers
are assigned to different banks. The last word of the I/O register locations (0xE - 0xF) is shared by all banks and can be
used to change the bank in use.
The following I/O Space Mapping Tables apply to 8, 16 or 32-bit bus products. Depending on the bus interface used and
byte enable signals (BE[3:0]N control byte access), each I/O access can be performed as an 8-bit, 16-bit, or 32-bit
operation. (The KSZ8862M is not limited to 8/16-bit performance and 32-bit read/write are also supported).
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