參數(shù)資料
型號： KBE00F005A
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 512Mb NAND*2 + 256Mb Mobile SDRAM*2
中文描述： 的512Mb的NAND * 2 256Mb的移動SDRAM * 2
文件頁數(shù)： 55/87頁
文件大小： 1353K
代理商： KBE00F005A
KBE00F005A-D411
MCP MEMORY
June 2005
55
Revision 1.0
D. DEVICE OPERATIONS
BANK ADDRESSES (BA0 ~ BA1)
This SDRAM is organized as two chips which has four indepen-
dent banks of 2,097,152 words x 32 bits memory arrays. The
BA0 ~ BA1 inputs are latched at the time of assertion of RAS and
CAS to select the bank to be used for the operation. The bank
addresses BA0 ~ BA1 are latched at bank active, read, write,
mode register set and precharge operations.
ADDRESS INPUTS (A0 ~ A12)
The 21 address bits are required to decode the 8,388,608 word
locations are multiplexed into 13 address input pins (A0 ~ A12).
The 13 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
(A0 ~ A7) are latched along with CAS, WE and BA0 ~ BA1 during
read or write command.
ADDRESSES of 512Mb
CLOCK (CLK)
The clock input is used as the reference for all SDRAM opera-
tions. All operations are synchronized to the positive going edge
of the clock.
The clock transitions must be monotonic between
V
IL
and V
IH
. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order to
function well Q perform and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro-
zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks are
in the idle state and CKE goes low synchronously with clock, the
SDRAM enters the power down mode from the next clock cycle.
The SDRAM remains in the power down mode ignoring the other
inputs as long as CKE remains low. The power down exit is syn-
chronous as the internal clock is suspended. When CKE goes
high at least "1CLK + tSS" before the high going edge of the
clock, then the SDRAM becomes active from the same clock
edge accepting all the input commands.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but is
needed to complete operations which require more than single
clock cycle like bank activate, burst read, auto refresh, etc. The
device deselect is also a NOP and is entered by asserting CS
high. CS high disables the command decoder so that RAS, CAS,
WE and all the address inputs are ignored.
相關(guān)PDF資料
PDF描述
KBE00F005A-D411 512Mb NAND*2 + 256Mb Mobile SDRAM*2
KBE00S003M 1Gb NAND*2 + 256Mb Mobile SDRAM*2
KBE00S003M-D411 1Gb NAND*2 + 256Mb Mobile SDRAM*2
KBJ408G 4.0A GLASS PASSIVATED BRIDGE RECTIFIER
KBJ4005G 4.0A GLASS PASSIVATED BRIDGE RECTIFIER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KBE00F005A-D411 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mb NAND*2 + 256Mb Mobile SDRAM*2
KBE00G003M 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:NAND 512Mb*2 + Mobile SDRAM 256Mb*2
KBE00G003M-D411 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:NAND 512Mb*2 + Mobile SDRAM 256Mb*2
KBE00S003M 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb NAND*2 + 256Mb Mobile SDRAM*2
KBE00S003M-D411 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb NAND*2 + 256Mb Mobile SDRAM*2
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