參數(shù)資料
型號(hào)： K4T1G044QC-ZCLE6
元件分類： DRAM
英文描述： 256M X 4 DDR DRAM, 0.45 ns, PBGA60
封裝： ROHS COMPLIANT, FBGA-60
文件頁(yè)數(shù)： 7/26頁(yè)
文件大?。?/td> 487K
代理商： K4T1G044QC-ZCLE6
DDR2 SDRAM
K4T1G044QC
K4T1G084QC
Rev. 1.1 June 2007
15 of 26
Note :
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS\, RDQS, RDQS\, LDQS, LDQS\, UDQS, and UDQS\. IDD values must be met with all combinations of EMRS
bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin
≤ VILAC(max)
HIGH is defined as Vin
≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control
signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including
masks or strobes.
For purposes of IDD testing, the following parameters are utilized
Detailed IDD7
The detailed timings are shown below for IDD7.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) and tFAW(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 8bank devices x4/ x8
-DDR2-400 3/3/3 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 4/4/4 : A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-667 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D
-DDR2-800 6/6/6 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
-DDR2-800 5/5/5 : A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 RA5 D A6 RA6 D A7 RA7 D D D
DDR2-800
DDR2-667
DDR2-533
DDR2-400
Units
Parameter
6-6-6
5-5-5
4-4-4
3-3-3
CL(IDD)
6
5
4
3
tCK
tRCD(IDD)
15
ns
tRC(IDD)
60
55
ns
tRRD(IDD)-x4/x8
7.5
ns
tRRD(IDD)-x16
10
ns
tCK(IDD)
2.5
3
3.75
5
ns
tRASmin(IDD)
45
40
ns
tRP(IDD)
15
ns
tRFC(IDD)
105
ns
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參數(shù)描述
K4T1G044QE 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM
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K4T1G044QE-HCLF7 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb E-die DDR2 SDRAM
K4T1G044QF 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Gb F-die DDR2 SDRAM
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